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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
Product Features
For a complete list of product features, see "Product Features" on page 11. The following features do require The following features do not require enabling software: enabling software: (R) Intel XScale Core -- Up to 533 MHz Encryption/Authentication (AES,DES,3DES,SHA-1,MD5) PCI Interface Two High-Speed, Serial Interfaces USB v1.1 Device Controller Three Network Processor Engines SDRAM Interface Up to two MII Interfaces High-Speed UART One UTOPIA-2 Interface Console UART Internal Bus Performance Monitoring Unit Multi-Channel HDLC 16 GPIOs Note: Refer to the Intel(R) IXP400 Software Programmer's Guide for information on Four Internal Timers which features are currently enabled. Packaging -- 492-pin PBGA Commercial/Extended Temperature
Typical Applications

High-Performance DSL Modem High-Performance Cable Modem Residential Gateway SME Router Network Printers

Control Plane Integrated Access Device (IAD) Set-Top Box Access Points (802.11a/b/g) Industrial Controllers
Document Number: 252479, Revision: 005
March 2005
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Intel may make changes to specifications and product descriptions at any time, without notice. Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. The Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. BunnyPeople, Celeron, Chips, Dialogic, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel Centrino logo, Intel logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon, PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Sound Mark, The Computer Inside, The Journey Inside, VTune, and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. All Rights Reserved.
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Contents
1.0 Introduction.................................................................................................................................... 9 1.1 1.2 About this Document ............................................................................................................ 9 Product Features ................................................................................................................ 11 1.2.1 Product Line Features ........................................................................................... 11 1.2.2 Processor Features ............................................................................................... 14 Functional Units .................................................................................................................. 20 2.1.1 Network Processor Engines (NPEs) ...................................................................... 20 2.1.2 Internal Bus............................................................................................................ 21 2.1.2.1 North AHB ..............................................................................................21 2.1.2.2 South AHB ............................................................................................. 22 2.1.2.3 APB Bus................................................................................................. 22 2.1.3 MII Interfaces ......................................................................................................... 22 2.1.4 UTOPIA 2 .............................................................................................................. 23 2.1.5 USB Interface ........................................................................................................ 23 2.1.6 PCI Controller ........................................................................................................ 23 2.1.7 SDRAM Controller ................................................................................................. 23 2.1.8 Expansion Bus ....................................................................................................... 24 2.1.9 High-Speed, Serial Interfaces ................................................................................ 24 2.1.10 High-Speed and Console UARTs .......................................................................... 25 2.1.11 GPIO ...................................................................................................................... 25 2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) .............................................. 25 2.1.13 Interrupt Controller ................................................................................................. 25 2.1.14 Timers .................................................................................................................... 26 2.1.15 AHB Queue Manager ............................................................................................ 26 Intel XScale(R) Core .............................................................................................................. 26 2.2.1 Super Pipeline ....................................................................................................... 27 2.2.2 Branch Target Buffer (BTB) ................................................................................... 28 2.2.3 Instruction Memory Management Unit (IMMU) ...................................................... 29 2.2.4 Data Memory Management Unit (DMMU) ............................................................. 29 2.2.5 Instruction Cache (I-Cache) ................................................................................... 29 2.2.6 Data Cache (D-Cache) .......................................................................................... 30 2.2.7 Mini-Data Cache .................................................................................................... 30 2.2.8 Fill Buffer (FB) and Pend Buffer (PB)..................................................................... 31 2.2.9 Write Buffer (WB)................................................................................................... 31 2.2.10 Multiply-Accumulate Coprocessor (CP0) ............................................................... 31 2.2.11 Performance Monitoring Unit (PMU)...................................................................... 32 2.2.12 Debug Unit ............................................................................................................. 32
2.0
Functional Overview ................................................................................................................... 15 2.1
2.2
3.0 4.0
Functional Signal Descriptions.................................................................................................. 33 Package and Pinout Information................................................................................................ 50 4.1 4.2 4.3 Package Description ...........................................................................................................50 Signal-Pin Descriptions....................................................................................................... 53 Package Thermal Specifications ........................................................................................ 81 4.3.1 Commercial Temperature ...................................................................................... 81
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4.3.2 5.0 5.1 5.2
Extended Temperature .......................................................................................... 81
Electrical Specifications ............................................................................................................. 82 Absolute Maximum Ratings ................................................................................................ 82 VCCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements .................................................. 82 5.2.1 VCCPLL1 Requirement ............................................................................................ 82 5.2.2 VCCPLL2 Requirement ............................................................................................ 83 5.2.3 VCCOSCP Requirement .......................................................................................... 83 5.2.4 VCCOSC Requirement ............................................................................................ 84 RCOMP Pin Requirements................................................................................................. 85 DC Specifications ............................................................................................................... 85 5.4.1 Operating Conditions ............................................................................................. 85 5.4.2 PCI DC Parameters ............................................................................................... 86 5.4.3 USB DC Parameters.............................................................................................. 86 5.4.4 UTOPIA-2 DC Parameters .................................................................................... 87 5.4.5 MII DC Parameters ................................................................................................ 87 5.4.6 MDIO DC Parameters............................................................................................ 88 5.4.7 SDRAM Bus DC Parameters................................................................................. 88 5.4.8 Expansion Bus DC Parameters ............................................................................. 88 5.4.9 High-Speed, Serial Interface 0 DC Parameters..................................................... 89 5.4.10 High-Speed, Serial Interface 1 DC Parameters..................................................... 89 5.4.11 High-Speed and Console UART DC Parameters .................................................. 90 5.4.12 GPIO DC Parameters ............................................................................................ 90 5.4.13 JTAG DC Parameters............................................................................................ 90 5.4.14 Reset DC Parameters............................................................................................ 91 AC Specifications................................................................................................................ 91 5.5.1 Clock Signal Timings ............................................................................................. 91 5.5.1.1 Processor Clock Timings ....................................................................... 91 5.5.1.2 PCI Clock Timings ................................................................................. 94 5.5.1.3 MII Clock Timings .................................................................................. 94 5.5.1.4 UTOPIA-2 Clock Timings....................................................................... 94 5.5.1.5 Expansion Bus Clock Timings ............................................................... 94 5.5.2 Bus Signal Timings ................................................................................................ 95 5.5.2.1 PCI ......................................................................................................... 95 5.5.2.2 USB Interface......................................................................................... 96 5.5.2.3 UTOPIA-2 .............................................................................................. 97 5.5.2.4 MII .......................................................................................................... 98 5.5.2.5 MDIO...................................................................................................... 99 5.5.2.6 SDRAM Bus......................................................................................... 100 5.5.2.7 Expansion Bus ..................................................................................... 101 5.5.2.8 High-Speed, Serial Interfaces .............................................................. 125 5.5.2.9 JTAG.................................................................................................... 127 5.5.3 Reset Timings...................................................................................................... 128 Power Sequence .............................................................................................................. 129 ICC and Total Average Power ........................................................................................... 131
5.3 5.4
5.5
5.6 5.7 6.0
Ordering Information................................................................................................................. 133
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Figures
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 Intel(R) IXP425 Network Processor Block Diagram ...................................................................... 15 Intel(R) IXP423 Network Processor Block Diagram ...................................................................... 16 Intel(R) IXP422 Network Processor Block Diagram ...................................................................... 17 Intel(R) IXP421 Network Processor Block Diagram ...................................................................... 18 Intel(R) IXP420 Network Processor Block Diagram ...................................................................... 19 Intel XScale(R) Core Block Diagram ............................................................................................. 27 492-Pin Lead PBGA Package .................................................................................................... 50 Package Markings ...................................................................................................................... 51 VCCPLL1 Power Filtering Diagram ............................................................................................... 83 VCCPLL2 Power Filtering Diagram ............................................................................................... 83 VCCOSCP Power Filtering Diagram ............................................................................................. 84 VCCOSC Power Filtering Diagram ............................................................................................... 84 RCOMP Pin External Resistor Requirements ............................................................................ 85 Typical Connection to a Crystal .................................................................................................. 93 Typical Connection to an Oscillator ............................................................................................ 93 PCI Output Timing ...................................................................................................................... 95 PCI Input Timing ......................................................................................................................... 95 UTOPIA-2 Input Timings............................................................................................................. 97 UTOPIA-2 Output Timings.......................................................................................................... 97 MII Output Timings ..................................................................................................................... 98 MII Input Timings ........................................................................................................................ 98 MDIO Output Timings ................................................................................................................. 99 MDIO Input Timings.................................................................................................................... 99 SDRAM Input Timings ..............................................................................................................100 SDRAM Output Timings ...........................................................................................................100 Signal Timing With Respect to Clock Rising Edge ...................................................................101 Intel(R) Multiplexed Read Mode ..................................................................................................102 Intel(R) Multiplexed Write Mode ..................................................................................................103 Intel(R) Simplex Read Mode........................................................................................................105 Intel(R) Simplex Write Mode........................................................................................................105 Motorola* Multiplexed Read Mode............................................................................................107 Motorola* Multiplexed Write Mode............................................................................................108 Motorola* Simplex Read Mode .................................................................................................110 Motorola* Simplex Write Mode .................................................................................................111 HPI-8 Mode Read Accesses.....................................................................................................113 HPI-8 Mode Write Accesses.....................................................................................................114 HPI-16 Multiplexed Write Mode ................................................................................................118 HPI-16 Multiplex Read Mode....................................................................................................120 HPI-16 Simplex Read Mode .....................................................................................................122 HPI-16 Simplex Write Mode .....................................................................................................124 High-Speed, Serial Timings ......................................................................................................125 Boundary-Scan General Timings..............................................................................................127 Boundary-Scan Reset Timings .................................................................................................127 Reset Timings...........................................................................................................................128 Power-Up Sequence Timing.....................................................................................................130
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Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Related Documents ...................................................................................................................... 9 Terminology and Acronyms .......................................................................................................... 9 Processor Features .................................................................................................................... 14 Processor Functions................................................................................................................... 20 Signal Type Definitions............................................................................................................... 33 SDRAM Interface........................................................................................................................ 34 PCI Controller ............................................................................................................................. 36 High-Speed, Serial Interface 0 ................................................................................................... 38 High-Speed, Serial Interface 1 ................................................................................................... 39 MII Interfaces.............................................................................................................................. 40 UTOPIA-2 Interface .................................................................................................................... 42 Expansion Bus Interface............................................................................................................. 44 UART Interfaces ......................................................................................................................... 45 USB Interface ............................................................................................................................. 46 Oscillator Interface...................................................................................................................... 46 GPIO Interface............................................................................................................................ 46 JTAG Interface ........................................................................................................................... 47 System Interface......................................................................................................................... 48 Power Interface .......................................................................................................................... 48 Part Numbers ............................................................................................................................. 51 Ball Map Assignment for the Intel(R) IXP425 Network Processor................................................. 53 Ball Map Assignment for the Intel(R) IXP422 Network Processor................................................. 60 Ball Map Assignment for the Intel(R) IXP421 Network Processor................................................. 67 Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor ............................................................................. 74 Operating Conditions.................................................................................................................. 85 PCI DC Parameters .................................................................................................................... 86 USB v1.1 DC Parameters........................................................................................................... 86 UTOPIA-2 DC Parameters ......................................................................................................... 87 MII DC Parameters..................................................................................................................... 87 MDIO DC Parameters ................................................................................................................ 88 SDRAM Bus DC Parameters...................................................................................................... 88 Expansion Bus DC Parameters.................................................................................................. 88 High-Speed, Serial Interface 0 DC Parameters.......................................................................... 89 High-Speed, Serial Interface 1 DC Parameters.......................................................................... 89 UART DC Parameters ................................................................................................................ 90 GPIO DC Parameters ................................................................................................................. 90 JTAG DC Parameters................................................................................................................. 90 PWRON_RESET_N DC Parameters ......................................................................................... 91 Device Clock Timings (Oscillator Reference) ............................................................................. 91 Device Clock Timings (Crystal Reference) ................................................................................. 92 PCI Clock Timings ...................................................................................................................... 94 MII Clock Timings ....................................................................................................................... 94 UTOPIA-2 Clock Timings ........................................................................................................... 94 Expansion Bus Clock Timings .................................................................................................... 94 PCI Bus Signal Timings .............................................................................................................. 96 UTOPIA-2 Input Timings Values ................................................................................................ 97 UTOPIA-2 Output Timings Values.............................................................................................. 97
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48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68
MII Output Timings Values ......................................................................................................... 98 MII Input Timings Values ............................................................................................................ 98 MDIO Timings Values................................................................................................................. 99 SDRAM Input Timings Values ..................................................................................................100 SDRAM Output Timings Values ...............................................................................................100 Signal Timing With Respect to Clock Rising Edge ...................................................................101 Intel(R) Multiplexed Mode Values................................................................................................104 Intel Simplex Mode Values .......................................................................................................106 Motorola* Multiplexed Mode Values .........................................................................................109 Motorola* Simplex Mode Values...............................................................................................112 HPI Timing Symbol Description ................................................................................................115 HPI-8 Mode Write Access Values.............................................................................................115 HPI-16 Multiplexed Write Accesses Values..............................................................................117 HPI-16 Multiplexed Read Accesses Values .............................................................................119 HPI-16 Simplex Read Accesses Values...................................................................................121 HPI-16 Simplex Write Accesses Values ...................................................................................123 High-Speed, Serial Timing Values............................................................................................126 Boundary-Scan Interface Timings Values ................................................................................127 Reset Timings Table Parameters .............................................................................................129 ICC and Total Average Power - Commercial Temperature Range...........................................131 ICC and Total Average Power - Extended Temperature Range...............................................132
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Revision History
Date Revision 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Description Rearranged product features lists in Section 1.2, "Product Features" Added two new columns to Table 3 to indicate Software Enable/Disable, and IXP423 network processor features Replaced network processor block diagrams: Figure 1, Figure 2, Figure 3, Figure 4, and Figure 5 Added new row for the IXP423 network processor to Table 4, "Processor Functions" Corrected the PCI_IDSEL definition in Table 7, "PCI Controller" Added pull-up resistor requirement for the ETH_MDIO pin in Table 10, "MII Interfaces" Added footnote to Table 18, "System Interface" regarding system level reset Added part number for IXP423 on Table 20, "Part Numbers" Added note 4 to Table 26, "PCI DC Parameters" Changed VIH "Minimum" parameter to 2.0 in Table 27, "USB v1.1 DC Parameters" (see the Intel(R) IXP4XX Product Line of Network Processors Specification Update (306428)); added note 2 Added new paragraph to Section 5.5.1.1, "Processor Clock Timings" regarding crystal oscillators application Added footnote regarding PLL operation at the lowest slew rate to Table 39, "Device Clock Timings (Oscillator Reference)" and Table 40, "Device Clock Timings (Crystal Reference)" Added footnote to Table 49, "MII Input Timings Values" and Table 50, "MDIO Timings Values" Inserted new Figure 26, "Signal Timing With Respect to Clock Rising Edge" Replaced Expansion Bus figures: Figure 26-Figure 40 Updated Table 53, "Signal Timing With Respect to Clock Rising Edge" Updated Trdsetup and Trdhold values in Table 54, Table 55, Table 56 and Table 57 Added footnotes to Table 61, "HPI-16 Multiplexed Read Accesses Values" Replaced Table 67, "ICC and Total Average Power - Commercial Temperature Range" , and inserted new Table 68, "ICC and Total Average Power - Extended Temperature Range"
March 2005
005
11. 12.
13. 14. 15. 16. 17. 18. 19.
June 2004
004
Updated Intel(R) product branding. Change bars are retained from the previous release of this document (-003). Incorporated specification changes, specification clarifications and document changes from the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Specification Update (252702-003). Incorporated specification changes, specification clarifications and document changes from the Intel(R) IXP42X Product Line of Network Processors Specification Update (252702-001). Incorporated information for the Intel(R) IXC1100 Control Plane Processor.
April 2004
003
May 2003
002
February 2003
001
Initial release of this document. Document reissued, without "Confidential" marking.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
1.0
1.1
Introduction
About this Document
This datasheet contains a functional overview of the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor, as well as mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications, and some bus functional wave forms for the device. Detailed functional descriptions -- other than parametric performance -- are published in the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual. Other related documents are shown in Table 1.
Table 1.
Related Documents
Document Title Intel(R) IXP4XX Product Line of Network Processors Specification Update Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual Intel(R) IXP400 Software Programmer's Guide Intel IXP400 Software Specification Update Intel XScale Core Developer's Manual Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines Intel XScale(R) Microarchitecture Technical Summary PCI Local Bus Specification, Rev. 2.2 Universal Serial Bus Specification, Revision 1.1 PC133 SDRAM Specification
(R) (R) (R)
Document # 306428 252480 252539 273795 273473 252817 -- -- -- --
Table 2.
Terminology and Acronyms
Acronym/ Terminology AAL AES AHB APB API Assert ATM AQM BTB CRC Deassert ATM Adaptation Layers Advanced Encryption Standard Advanced High-Performance Bus Advanced Peripheral Bus Application Program Interface The logically active value of a signal or bit. Asynchronous Transmission Mode AHB Queue Manager Branch Target Buffer Cyclical Redundancy Check The logically inactive value of a signal or bit. Description
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 2.
Terminology and Acronyms (Continued)
Acronym/ Terminology DDR DES DMA DSP E1 FIFO GCI GPIO HDLC HPI HSS LSb LSB MAC MDIO MII MMU MSb MSB NPE PCI PHY Reserved RX SRAM SDRAM T1 TX UART USB UTOPIA WAN Double Data Rate Data-Encryption Standard Direct Memory Access Digital Signal Processor Euro 1 trunk line First In First Out General Circuit Interface General-purpose input/output High-level Data Link Control (Texas Instruments*) Host Port Interfaces High-Speed Serial (port) Least-Significant bit Least-Significant Byte Media Access Controller Management Data Input/Output Media-Independent Interface Memory Management Unit Most-Significant bit Most-Significant Byte Network Processor Engine Peripheral Component Interconnect Physical Layer (Layer 1) Interface A field that may be used by an implementation. Software should not modify reserved fields or depend on any values in reserved fields. Receive (HSS is receiving from off-chip) Static Random Access Memory Synchronous Dynamic Random Access Memory Type 1 trunk line Transmit (HSS is transmitting off-chip) Universal Asynchronous Receiver-Transmitter Universal Serial Bus Universal Test and Operations PHY Interface for ATM Wide Area Network Description
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
1.2
1.2.1
Product Features
Product Line Features
Table 3 on page 14 describes which features apply to the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor.
* Intel XScale(R) Core (compliant with ARM* architecture)
-- High-performance processor based on Intel XScale(R) Microarchitecture -- Seven/eight-stage Intel(R) Super-Pipelined RISC Technology -- Management unit * 32-entry, data memory management unit * 32-entry, instruction memory management unit * 32-Kbyte, 32-way, set associative instruction cache * 32-Kbyte, 32-way, set associative data cache * 2-Kbyte, two-way, set associative mini-data cache * 128-entry, branch target buffer * Eight-entry write buffer * Four-entry fill and pend buffers -- Clock speeds: * 266 MHz * 400 MHz * 533 MHz -- ARM* Version V5TE Compliant -- Intel(R) Media Processing Technology Multiply-accumulate coprocessor -- Debug unit Accessible through JTAG port
* PCI interface
-- 32-bit interface -- Selectable clock * 33 MHz clock output derived from either GPIO14 or GPIO15 * 33 and 66 MHz clock input -- PCI Local Bus Specification, Rev. 2.2 compatible -- PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs) -- Host/option capable -- Master/target capable -- Two DMA channels
* USB v 1.1 device controller
-- Full-speed capable -- Embedded transceiver Datasheet Document Number: 252479, Revision: 005 March 2005 11
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
-- 16 endpoints
* SDRAM interface
-- 32-bit data -- 13-bit address -- 133 MHz -- Up to eight open pages simultaneously maintained -- Programmable auto-refresh -- Programmable CAS/data delay -- Support for 8 MB, minimum, up to 256 MB maximum
* Expansion interface
-- 24-bit address -- 16-bit data -- Eight programmable chip selects -- Supports Intel/Motorola* microprocessors * Multiplexed-style bus cycles * Simplex-style bus cycles
* DSP support for:
-- Texas Instruments* DSPs supporting HPI-8 bus cycles * Texas Instruments DSPs supporting HPI-16 bus cycles
* High-speed/Console UARTs
-- 1,200 baud to 921 Kbaud -- 16550 compliant -- 64-byte Tx and Rx FIFOs -- CTS and RTS modem control signals
* Internal bus performance monitoring unit
-- Seven 27-bit event counters -- Monitoring of internal bus occurrences and duration events
* 16 GPIOs * Four internal timers * Packaging
-- 492-pin PBGA -- Commercial temperature (0 to +70 C) -- Extended temperature (-40 to +85 C) The following features can be enabled by software, consult the Intel(R) IXP400 Software Programmer's Guide to determine if a feature can be enabled for a particular product.
* Three network processor engines (NPEs)
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Used to offload typical Layer-2 networking functions such as: -- Ethernet filtering -- ATM SARing -- HDLC
* Encryption/Authentication
-- DES -- DES 3 -- AES 128-bit and 256-bit
* Two MII interfaces
-- 802.3 MII interfaces -- Single MDIO interface to control both MII interfaces
* UTOPIA-2 Interface
-- Eight-bit interface -- Up to 33 MHz clock speed -- Five transmit and five receive address lines
* Two high-speed, serial interfaces
-- Six-wire -- Supports speeds up to 8.192 MHz -- Supports connection to T1/E1 framers -- Supports connection to CODEC/SLICs -- Eight HDLC Channels
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1.2.2
Table 3.
Feature
Processor Features
Processor Features
Requires Enabling Software (Note 1) Intel(R) IXP425 Network Processor B0 Step 266/400/533 Yes X X X Yes Yes Yes Yes X X X X X X 16-bit, 66 MHz 32-bit, 133 MHz Yes X Intel(R) IXP423 Network Processor Intel(R) IXP422 Network Processor Intel(R) IXP421 Network Processor Intel(R) IXP420 Network Processor Intel(R) IXC1100 Control Plane Processor 266/400/533
Processor Speed (MHz) UTOPIA 2 GPIO UART 0/1 HSS 0 HSS 1 MII 0 MII 1 USB PCI Expansion Bus SDRAM AES / DES / DES3 MultiChannel HDLC SHA-1 / MD-5 Commercial Temperature Extended Temperature
266 X X X X X X X X X 16-bit, 66 MHz 32-bit, 133 MHz
266
266 X
266/400/533
X X
X X X X
X X
X X
X X X X 16-bit, 66 MHz 32-bit, 133 MHz X
X
X X
X X X X 16-bit, 66 MHz 32-bit, 133 MHz
X X 16-bit, 66 MHz 32-bit, 133 MHz
X X 16-bit, 66 MHz 32-bit, 133 MHz
Yes
8
8
8
Yes
X X X X
X X X X X (Note 2) X X
Notes: 1. The features marked "Yes" require enabling software. Please refer to the Intel(R) IXP400 Software Programmer's Guide to determine if the feature is enabled. 2. Only the 266 MHz version of the Intel(R) IXP420 Network Processor supports extended temperature.
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2.0
Functional Overview
The Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are compliant with the ARM* Version 5TE instruction-set architecture (ISA). The Intel(R) IXP42X product line and IXC1100 control plane processors are designed with Intel 0.18- production semiconductor process technology. This process technology -- along with the compactness of the Intel XScale core, the ability to simultaneously process up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces -- enables the IXP42X product line and IXC1100 control plane processors to operate over a wide range of low-cost networking applications, with industry-leading performance. As indicated in Figure 1 through Figure 5, the Intel(R) IXP42X product line and IXC1100 control plane processors combine many features with the Intel XScale core to create a highly integrated processor applicable to LAN/WAN-based networking applications in addition to other embedded networking applications. This section briefly describes the main features of the product. For detailed functional descriptions, see the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual.
Figure 1.
Intel(R) IXP425 Network Processor Block Diagram
HSS-1
HSS-0
UTOPIA 2
UTOPIA (Max 24 xDSL PHYs) AAL, HSS, HDLC
MII-0
WAN/Voice NPE
Ethernet MAC
MII-1
Ethernet NPE A Ethernet NPE B
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet MAC SHA-1/MD5, DES/3DES, AES
North AHB Arbiter
Queue Manager 8 KB SRAM
SDRAM Controller 8 - 256 MB
32-Bit
UART Interrupt 921Kbaud Controller
Timers
North/South AHB Bridge
South AHB Arbiter
66.66 MHz Advanced Peripheral Bus
AHB/APB Bridge
133.32 MHz x 32 bits South Advance High-Performance Bus
UART GPIO 921Kbaud Controller
16 GPIO
USB Device V1.1
PMU (AHB) Test Logic Unit
JTAG
266/400/533 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache
Intel XScale(R) Core
PCI Controller
32-Bit
Expansion Bus Controller
16-Bit
B1563-04
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Figure 2.
Intel(R) IXP423 Network Processor Block Diagram
HSS-1
HSS-0
UTOPIA-2
UTOPIA (Max 24 xDSL PHYs) AAL, HSS, HDLC
MII-0
WAN/Voice NPE
Ethernet MAC
MII-1
Ethernet NPE A Ethernet NPE B
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet MAC
North AHB Arbiter
Queue Manager 8 KB SRAM
SDRAM Controller 8 - 256 MB
32-Bit
UART Interrupt 921Kbaud Controller
Timers
North/South AHB Bridge
South AHB Arbiter
66.66 MHz Advanced Peripheral Bus
AHB/APB Bridge
133.32 MHz x 32 bits South Advance High-Performance Bus
UART GPIO 921Kbaud Controller
16 GPIO
USB Device V1.1
PMU (AHB) Test Logic Unit
JTAG
266 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache
Intel XScale(R) Core
PCI Controller
32-Bit
Expansion Bus Controller
16-Bit
B4285-02
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Figure 3.
Intel(R) IXP422 Network Processor Block Diagram
MII-0
Ethernet MAC
MII-1
Ethernet NPE A
133.32 MHz x 32 bits North Advance High-Performance Bus
Ethernet MAC SHA-1/MD5, DES, 3DES, AES
UART Interrupt 921Kbaud Controller
Ethernet NPE B
Queue Status Bus
North AHB Arbiter
Queue Manager 8 KB SRAM
SDRAM Controller 8 - 256 MB
32-Bit
Timers
North/South AHB Bridge
South AHB Arbiter
66.66 MHz Advanced Peripheral Bus
AHB/APB Bridge
133.32 MHz x 32 bits South Advance High-Performance Bus
UART GPIO 921Kbaud Controller
16 GPIO
USB Device V1.1
PMU (AHB) Test Logic Unit
JTAG
266 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache
Intel XScale Core Intel XScale(R)(R)Core
PCI Controller
32-Bit
Expansion Bus Controller
16-Bit
B1566-04
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Figure 4.
Intel(R) IXP421 Network Processor Block Diagram
HSS-1
HSS-0
UTOPIA 2
UTOPIA (Max 4 xDSL PHYs) AAL, HSS
MII-0
WAN/Voice NPE
133.32 MHz x 32 bits North Advance High-Performance Bus
Ethernet MAC
Ethernet NPE A
Queue Status Bus
North AHB Arbiter
Queue Manager 8 KB SRAM
SDRAM Controller 8 - 256 MB
32-Bit
UART Interrupt 921Kbaud Controller
Timers
North/South AHB Bridge
South AHB Arbiter
66.66 MHz Advanced Peripheral Bus
AHB/APB Bridge
133.32 MHz x 32 bits South Advance High-Performance Bus
UART GPIO 921Kbaud Controller
16 GPIO
USB Device V1.1
PMU (AHB) Test Logic Unit
JTAG
266 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache
Intel XScale Core Intel XScale(R)(R)Core
PCI Controller
32-Bit
Expansion Bus Controller
16-Bit
B1565-04
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Figure 5.
Intel(R) IXP420 Network Processor Block Diagram
MII-0
Ethernet MAC
MII-1
Ethernet NPE A Ethernet NPE B
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet MAC
North AHB Arbiter
Queue Manager 8 KB SRAM
SDRAM Controller 8 - 256 MB
32-Bit
UART Interrupt 921Kbaud Controller
Timers
North/South AHB Bridge
South AHB Arbiter
66.66 MHz Advanced Peripheral Bus
AHB/APB Bridge
133.32 MHz x 32 bits South Advance High-Performance Bus
UART GPIO 921Kbaud Controller
16 GPIO
USB Device V1.1
PMU (AHB) Test Logic Unit
JTAG
266/400/533 MHz 32 KB Data Cache 32 KB Instruction Cache 2 KB Mini-Data Cache
Intel XScale Core Intel XScale(R)(R)Core
PCI Controller
32-Bit
Expansion Bus Controller
16-Bit
B1564-04
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2.1
Functional Units
The following sections briefly describe the functional units and their interaction in the system. For more detailed information, refer to the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual. Unless otherwise specified, the functional descriptions apply to all processors in the IXP42X product line and IXC1100 control plane processors. Refer to Table 3 on page 14 and Figure 1 on page 15 through Figure 5 for specific information on supported interfaces
2.1.1
Network Processor Engines (NPEs)
The network processor engines (NPEs) are dedicated-function processors containing hardware coprocessors integrated into the IXP42X product line and IXC1100 control plane processors. The NPEs are used to off-load processing functions required by the Intel XScale core. These NPEs are high-performance, hardware-multi-threaded processors with additional localhardware-assist functionality used to off-load highly processor-intensive functions such as MII (MAC), CRC checking/generation, AAL 2, AES, DES, SHA-1, and MD5. All instruction code for the NPEs are stored locally with a dedicated instruction memory bus and dedicated data memory bus. These NPEs support processing of the dedicated peripherals that can include:
* A Universal Test and Operation PHY Interface for ATM (UTOPIA) 2 interface * Two High-Speed Serial (HSS) interfaces * Two Media-Independent Interfaces (MII)
Table 4 specifies which devices, in the IXP42X product line and IXC1100 control plane processors, have which of these capabilities. Table 4. Processor Functions
Device Intel(R) IXP425 Network Processor, B-Step Intel(R) IXP423 Network Processor Intel(R) IXP422 Network Processor Intel(R) IXP421 Network Processor Intel(R) IXP420 Network Processor Intel(R) IXC1100 Control Plane Processor X X UTOPIA X X HSS X X MII 0 X X X X X X X X MII 1 X X X X 8 AES / DES / Multi-Channel SHA-1 / DES3 HDLC MD-5 X 8 8 X X
The NPE core is a hardware-multi-threaded processor engine that is used to accelerate functions that are difficult to achieve high performance in a standard RISC processor. Each NPE core is a 133 MHz processor core that has self-contained instruction memory and self-contained data memory that operate in parallel.
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In addition to having separate instruction/data memory and local-code store, the NPE core supports hardware multi-threading with support for multiple contexts. The support of hardware multithreading creates an efficient processor engine with minimal processor stalls due to the ability of the processor core to switch contexts in a single clock cycle, based on a prioritized/preemptive basis. The prioritized/preemptive nature of the context switching allows time-critical applications to be implemented in a low-latency fashion -- which is required when processing multi-media applications. The NPE core also connects several hardware-based coprocessors that are used to implement functions that are difficult for a processor to implement. These functions include:
* Serialization/De-serialization * DES/3DES/AES * MD5
* CRC checking/generation * SHA-1 * HDLC bit stuffing/de-stuffing
These coprocessors are implemented in hardware, enabling the coprocessors and the NPE processor core to operate in parallel. The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the Intel XScale core to be utilized for application purposes. The multi-processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the Intel XScale core.
2.1.2
Internal Bus
The internal bus architecture of the IXP42X product line and IXC1100 control plane processors is designed to allow parallel processing to occur and to isolate bus utilization, based on particular traffic patterns. The bus is segmented into three major buses: the North AHB, South AHB, and APB.
2.1.2.1
North AHB
The North AHB is a 133.32 MHz, 32-bit bus that can be mastered by the NPEs. The targets of the North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB bridge allows the NPEs to access the peripherals and internal targets on the South AHB. Data transfers by the NPEs on the North AHB to the South AHB are targeted predominately to the queue manager. Transfers to the AHB/AHB bridge may be "posted," when writing, or "split," when reading. When a transaction is "posted," a master on the North AHB requests a write to a peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write request will be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete the write on the South AHB, when it can obtain access to the peripheral on the South AHB. The North AHB is released to complete another transaction. When a transaction is "split," a master on the North AHB requests a read of a peripheral on the South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB bridge will complete the read on the South AHB, when it can obtain access to the peripheral on the South AHB.
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Once the AHB/AHB bridge has obtained the read information from the peripheral on the South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/AHB bridge has the data for the master that requested the "split" transfer. The master on the North AHB -- that requested the split transfer -- will arbitrate for the North AHB and transfer the read data from the AHB/AHB bridge. The North AHB is released to complete another transaction while the North AHB master -- that requested the "split" transfer -- waits for the data to arrive. These "posting" and "splitting" transfers allow control of the North AHB to be given to another master on the North AHB -- enabling the North AHB to achieve maximum efficiency. Transfers to the AHB/AHB bridge are considered to be small and infrequent, relative to the traffic passed between the NPEs on the North AHB and the SDRAM.
2.1.2.2
South AHB
The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale(R) Core, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB bridge. Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the APB.
2.1.2.3
APB Bus
The APB Bus is a 66.66 MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be mastered by the AHB/APB bridge only. The targets of the APB bus can be:
* High-speed UART interface * USB v1.1 interface * Internal bus performance monitoring unit
(IBPMU)
* Console UART interface * All NPEs * Interrupt controller * Timers
* GPIO
The APB interface is also used as an alternate-path interface to the NPEs and is used for NPE code download and configuration.
2.1.3
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated into most of the IXP42X product line and IXC1100 control plane processors with separate media-access controllers and independent network processing engines. (See Table 4 on page 20.) The independent NPEs and MACs allow parallel processing of data traffic on the MII interfaces and off-loading of processing required by the Intel XScale(R) Core. The IXP42X product line and IXC1100 control plane processors are compliant with the IEEE, 802.3 specification. In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane processors include a single management data interface that is used to configure and control PHY devices that are connected to the MII interface.
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2.1.4
UTOPIA 2
The integrated, UTOPIA-2 interface works with a network processing engine, for several of the IXP42X product line and IXC1100 control plane processors. (See Table 4 on page 20.) The UTOPIA-2 interface supports a single- or a multiple-physical-interface configuration with cell-level or octet-level handshaking. The network processing engine handles segmentation and reassembly of ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA-2 interface, off-loading processor overhead required by the Intel XScale(R) Core. The IXP42X product line and IXC1100 control plane processors are compliant with the ATM Forum, UTOPIA Level-2 Specification, Revision 1.0.
2.1.5
USB Interface
The integrated USB 1.1 interface is a device-only controller. The interface supports full-speed operation and 16 endpoints and includes an integrated transceiver. There are:
* * * * 2.1.6
Six isochronous endpoints (three input and three output) One control endpoints Three interrupt endpoints Six bulk endpoints (three input and three output)
PCI Controller
The IXP42X product line and IXC1100 control plane processors' PCI controller is compatible with the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as either a host or an option (i.e., not the Host) For more information on PCI Controller support and configuration see the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual.
2.1.7
SDRAM Controller
The memory controller manages the interface to external SDRAM memory chips. The interface:
* Operates at 133.32 MHz (which is 4 * OSC_IN input pin.) * Supports eight open pages simultaneously * Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte
The memory controller only supports 32-bit memory. If a x16 memory chip is used, a minimum of two memory chips would be required to facilitate the 32-bit interface required by the IXP42X product line and IXC1100 control plane processors. A maximum of four SDRAM memory chips may be attached to the processors. For more information on SDRAM support and configuration see the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual. The memory controller internally interfaces to the North AHB and South AHB with independent interfaces. This architecture allows SDRAM transfers to be interleaved and pipelined to achieve maximum possible efficiency. Datasheet Document Number: 252479, Revision: 005 March 2005 23
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The maximum burst size supported to the SDRAM interface is eight 32-bit words. This burst size allows the best efficiency/fairness performance between accesses from the North AHB and the South AHB.
2.1.8
Expansion Bus
The expansion interface allows easy and -- in most cases -- glue-less connection to peripheral devices. It also provides input information for device configuration after reset. Some of the peripheral device types are flash, ATM control interfaces, and DSPs used for voice applications. (Some voice configurations can be supported by the HSS interfaces and the Intel XScale(R) Core, implementing voice-compression algorithms.) The expansion bus interface is a 16-bit interface that allows an address range of 512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip selects. Accesses to the expansion bus interface consists of five phases. Each of the five phases can be lengthened or shortened by setting various configuration registers on a per-chip-select basis. This feature allows the IXP42X product line and IXC1100 control plane processors to connect to a wide variety of peripheral devices with varying speeds. The expansion bus interface supports Intel or Motorola* microprocessor-style bus cycles. The bus cycles can be configured to be multiplexed address/data cycles or separate address/data cycles for each of the eight chip-selects. Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments HPI-8 or HPI-16 style accesses for DSPs. The expansion bus interface is an asynchronous interface to externally connected chips. However, a clock must be supplied to the IXP42X product line and IXC1100 control plane processors' expansion bus interface for the interface to operate. This clock can be driven from GPIO 15 or an external source. The maximum clock rate that the expansion bus interface can accept is 66.66 MHz. At the de-assertion of reset, the 24-bit address bus is used to capture configuration information from the levels that are applied to the pins at this time. External pull-up/pull-down resistors are used to tie the signals to particular logic levels. (For additional details, see "Package and Pinout Information" on page 50.)
2.1.9
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer speeds from 512 KHz to 8.192 MHz, for some models of the IXP42X product line and IXC1100 control plane processors. (See Table 4 on page 20.) Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the IXP42X product line and IXC1100 control plane processors. The high-speed, serial interfaces are capable of supporting various protocols, based on the implementation of the code developed for the network processor engine core. For a list of supported protocols, see the Intel(R) IXP400 Software Programmer's Guide.
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2.1.10
High-Speed and Console UARTs
The UART interfaces are 16550-compliant UARTs with the exception of transmit and receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes required by the 16550 UART specification. The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The interface support configurations of:
* Five, six, seven, or eight data-bit transfers * One or two stop bits * Even, odd, or no parity
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also are available with the interface for hardware flow control.
2.1.11
GPIO
There are 16 GPIO pins supported by the IXP42X product line and IXC1100 control plane processors. GPIO pins 0 through 13 can be configured to be general-purpose input or generalpurpose output. Additionally, GPIO pins 0 through 12 can be configured to be an interrupt input. GPIO Pin 14 can be configured similar to GPIO pin 13 or as a clock output. The output-clock configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 14 is configured as an input, upon reset. GPIO Pin 15 can be configured similar to GPIO pin 13 or as a clock output. The output-clock configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles. GPIO Pin 15 is configured as a clock output, upon reset. GPIO Pin 15 can be used to clock the expansion interface, after reset.
2.1.12
Internal Bus Performance Monitoring Unit (IBPMU)
The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit counters that may be used to capture predefined durations or occurrence events on the North AHB, South AHB, or SDRAM controller page hits/misses.
2.1.13
Interrupt Controller
The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to allow an extension of the Intel XScale(R) Core FIQ and IRQ interrupt sources. These sources can originate from some external GPIO pins or internal peripheral interfaces. The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining interrupts are prioritized in ascending order. For example, Interrupt 8 has a higher priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.
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2.1.14
Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task scheduling and prevent software lock-ups. The device has four 32-bit counters:
* Watch-Dog Timer 2.1.15 AHB Queue Manager
* Timestamp Timer
* Two general-purpose timers
The AHB Queue Manager (AQM) provides queue functionality for various internal blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also implements the status flags and pointers required for each queue. The AQM manages 64 independent queues. Each queue is configurable for buffer and entry size. Additionally status flags are maintained for each queue. The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale core (or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale core. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM. Individual queue status for queues 0-31 is communicated to the NPEs via the flag bus. Combined queue status for queues 32-63 are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-31 and one for queues 32-63, provide status interrupts to the Intel XScale core.
2.2
Intel XScale(R) Core
The Intel XScale(R) Core technology is compliant with the ARM* Version 5TE instruction-set architecture (ISA). The Intel XScale core -- shown in Figure 6 -- is designed with Intel 0.18- production semiconductor process technology. This process technology enables the Intel XScale core to operate over a wide speed and power range, producing industry-leading mW/MIPS performance. Intel XScale core features include:
* Seven/eight-stage super-pipeline promotes high-speed, efficient core performance * 128-entry branch target buffer keeps pipeline filled with statistically correct branch choices * 32-entry instruction memory-management unit for logical-to-physical address translation,
access permissions, I-cache attributes permissions, D-cache attributes
* 32-entry data-memory management unit for logical-to-physical address translation, access * 32-Kbyte instruction cache can hold entire programs, preventing core stalls caused by multicycle memory accesses
* 32-Kbyte data cache reduces core stalls caused by multi-cycle memory accesses * 2-Kbyte mini-data cache for frequently changing data streams avoids "thrashing" of the Dcache
* Four-entry fill-and-pend buffers to promote core efficiency by allowing "hit-under-miss"
operation with data caches
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* Eight-entry write buffer allows the core to continue execution while data is written to memory * Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD multiplies with
40-bit accumulation for efficient, high-quality media and signal processing
* Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle
counter for analysis of hit rates, etc. This PMU is for the Intel XScale core only. An additional PMU is supplied for monitoring of internal bus performance. change messages) to debug programs
* JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flowFigure 6. Intel XScale(R) Core Block Diagram
Branch Target Cache
FIQ IRQ Interrupt Request Instruction
M Instruction Cache M 32 KB U Data Cache 32 KB Mini-Data Cache 2 KB
Execution Core
Coprocessor Interface Data Address Data
South AHB Bus
M M U
Multiply Accumulate
System Management
Debug/ PMU
JTAG
A9568-02
2.2.1
Super Pipeline
The super pipeline is composed of integer, multiply-accumulate (MAC), and memory pipes. The integer pipe has seven stages:
* * * * * * *
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The memory pipe has eight stages:
* The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
. . . then finish with the following memory stages:
* Data Cache 1 * Data Cache 2 * Data Cache Writeback
The MAC pipe has six to nine stages:
* The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
. . . then finish with the following MAC stages: MAC 1 MAC 2 MAC 3 MAC 4 Data Cache Writeback
* * * * *
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3, and/or MAC 4 are bypassed. Deep pipes promote high instruction execution rates only when a means exists to successfully predict the outcome of branch instructions. The branch target buffer provides such a means.
2.2.2
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the target address associated with the branch instruction, and a previous history of the branch being taken or not taken. The history is recorded as one of four states:
* Strongly taken
* Weakly taken
* Weakly not taken
* Strongly not taken
The BTB can be enabled or disabled via Coprocessor 15, Register 1. When the address of the branch instruction hits in the BTB and its history is strongly or weakly taken, the instruction at the branch target address is fetched. When its history is strongly or weakly not-taken, the next sequential instruction is fetched. In either case the history is updated. Data associated with a branch instruction enters the BTB the first time the branch is taken. This data enters the BTB in a slot with a history of strongly not-taken (overwriting previous data when present). Successfully predicted branches avoid any branch-latency penalties in the super pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency penalty in the super pipeline.
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2.2.3
Instruction Memory Management Unit (IMMU)
For instruction pre-fetches, the IMMU controls logical-to-physical address translation, memory access permissions, memory-domain identifications, and attributes (governing operation of the instruction cache). The IMMU contains a 32-entry, fully associative instruction-translation, lookaside buffer (ITLB) that has a round-robin replacement policy. ITLB entries zero through 30 can be locked. When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the ITLB. The descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes governing operation of the I-cache. The IMMU then continues the instruction pre-fetch by using the address translation just entered into the ITLB. When an instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch using the address translation already resident in the ITLB. Access permissions for each of up to 16 memory domains can be programmed. When an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together.
2.2.4
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes (governing operation of the data cache or mini-data cache and write buffer). The DMMU contains a 32-entry, fully associative datatranslation, look-aside buffer (DTLB) that has a round-robin replacement policy. DTLB entries 0 through 30 can be locked. When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk mechanism that fetches an associated descriptor from memory and loads it into the DTLB. The descriptor contains information for logical-to-physical address translation, memory-access permissions, memory-domain identifications, and attributes (governing operation of the D-cache or mini-data cache and write buffer). The DMMU continues the data fetch by using the address translation just entered into the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the address translation already resident in the DTLB. Access permissions for each of up to 16 memory domains can be programmed. When a data fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a data abort is sent to the core for exception processing. The IMMU and DMMU can be enabled or disabled together.
2.2.5
Instruction Cache (I-Cache)
The I-cache can contain high-use, multiple-code segments or entire programs, allowing the core access to instructions at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory. The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line of instructions (eight 32-bit words and one parity bit per word), and a line-valid bit. For each of the 32 sets, 0 through 28 ways can be locked. Unlocked ways are replaceable via a round-robin policy.
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The I-cache can be enabled or disabled. Attribute bits within the descriptors -- contained in the ITLB of the IMMU -- provide some control over an enabled I-cache. When a needed line (eight 32-bit words) is not present in the I-cache, the line is fetched (critical word first) from memory via a two-level, deep-fetch queue. The fetch queue allows the next instruction to be accessed from the I-cache, but only when its data operands do not depend on the execution results of the instruction being fetched via the queue.
2.2.6
Data Cache (D-Cache)
The D-cache can contain high-use data such as lookup tables and filter coefficients, allowing the core access to data at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory. The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and one valid bit. For each of the 32 sets, zero through 28 ways can be locked, unlocked, or used as local SRAM. Unlocked ways are replaceable via a round-robin policy. The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute bits within the descriptors, contained in the DTLB of the DMMU, provide significant control over an enabled D-cache. These bits specify cache operating modes such as read and write allocate, write-back, write-through, and D-cache versus mini-data cache targeting. The D-cache (and mini-data cache) work with the load buffer and pend buffer to provide "hitunder-miss" capability that allows the core to access other data in the cache after a "miss" is encountered. The D-cache (and mini-data cache) works in conjunction with the write buffer for data that is to be stored to memory.
2.2.7
Mini-Data Cache
The mini-data cache can contain frequently changing data streams such as MPEG video, allowing the core access to data streams at core frequencies. This prevents core stalls caused by multi-cycle accesses to external memory. The mini-data cache relieves the D-cache of data "thrashing" caused by frequently changing data streams. The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains two ways and each way contains a tag address, a cache line (32 bytes with one parity bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and a valid bit. The mini-data cache uses a round-robin replacement policy, and cannot be locked. The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute bits contained within a coprocessor register specify operating modes write and/or read allocate, writeback, and write-through. The mini-data cache (and D-cache) work with the load buffer and pend buffer to provide "hitunder-miss" capability that allows the core to access other data in the cache after a "miss" is encountered. The mini-data cache (and D-cache) works in conjunction with the write buffer for data that is to be stored to memory.
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2.2.8
Fill Buffer (FB) and Pend Buffer (PB)
The four-entry fill buffer (FB) works with the core to hold non-cacheable loads until the bus controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and mini-data cache to provide "hit-under-miss" capability, allowing the core to seek other data in the caches while "miss" data is being fetched from memory. The FB can contain up to four unique "miss" addresses (logical), allowing four "misses" before the core is stalled. The PB holds up to four addresses (logical) for additional "misses" to those addresses that are already in the FB. A coprocessor register can specify draining of the fill and pend (write) buffers.
2.2.9
Write Buffer (WB)
The write buffer (WB) holds data for storage to memory until the bus controller can act on it. The WB is eight entries deep, where each entry holds 16 bytes. The WB is constantly enabled and accepts data from the core, D-cache, or mini-data cache. Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled. When coalescing is disabled, stores to memory occur in program order regardless of the attribute bits within the descriptors located in the DTLB. When coalescing is enabled, the attribute bits within the descriptors located in the DTLB are examined to determine when coalescing is enabled for the destination region of memory. When coalescing is enabled in both CP15, R1 and the DTLB, data entering the WB can coalesce with any of the eight entries (16 bytes) and be stored to the destination memory region, but possibly out of program order. Stores to a memory region specified to be non-cacheable and non-bufferable by the attribute bits within the descriptors located in the DTLB causes the core to stall until the store completes. A coprocessor register can specify draining of the write buffer.
2.2.10
Multiply-Accumulate Coprocessor (CP0)
For efficient processing of high-quality, media-and-signal-processing algorithms, CP0 provides 40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD), and 32 x 32 signed multiplies. Special MAR and MRA instructions are implemented to move the 40-bit accumulator to two core-general registers (MAR) and move two core-general registers to the 40-bit accumulator (MRA). The 40-bit accumulator can be stored or loaded to or from D-cache, mini-data cache, or memory using two STC or LDC instructions. The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/low, high/ low, or low/high 16 bits of a 32-bit core general register (multiplier) and another 32-bit core general register (multiplicand) to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-bit accumulator. Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and low/low 16-bits of a packed 32-bit, core-general register (multiplier) and another packed 32-bit, coregeneral register (multiplicand) to produce two 16-bits products that are both sign-extended to 40 bits and added to the 40-bit accumulator. The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, core-general register (multiplier) and another 32-bit, core-general register (multiplicand) to produce a 64-bit product where the 40 LSBs are added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32 multiply-accumulate instructions complete in a single cycle.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
2.2.11
Performance Monitoring Unit (PMU)
The performance monitoring unit contains two 32-bit, event counters and one 32-bit, clock counter. The event counters can be programmed to monitor I-cache hit rate, data caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and instruction execution count.
2.2.12
Debug Unit
The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1 JTAG port consists of a test access port (TAP) controller, boundary-scan register, instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#. The debug unit -- when used with debugger application code running on a host system outside of the Intel XScale core -- allows a program, running on the Intel XScale core, to be debugged. It allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine. Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the core's state, coprocessor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware-instruction, break point registers; two hardware, data-breakpoint registers; and a hardware, data-breakpoint control register. The second data-breakpoint register can be alternatively used as a mask register for the first data-breakpoint register. A 256-entry trace buffer provides the ability to capture control flow messages or addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the JTAG port to the miniinstruction cache (the I-cache has a 2-Kbyte, mini-instruction cache to hold a debug handler).
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3.0
Functional Signal Descriptions
Listed in the signal definition tables -- starting at Table 6 "SDRAM Interface" on page 34 -- are pull-up an pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application. These external resistor requirements are only needed if the particular model of Intel(R) IXP42X product line and IXC1100 control plane processors has the particular interface enabled and the interface is not required in the application.
Warning:
All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V tolerant. Disabled features, within the IXP42X product line and IXC1100 control plane processors, do not require external resistors as the processor will have internal pull-up or pull-down resistors enabled as part of the disabled interface. Table 5 presents the legend for interpreting the Type field in the other tables in this section of the document. To determine which interfaces are not enabled within the IXP42X product line and IXC1100 control plane processors, see Table 3 on page 14. Signal Type Definitions
Symbol I O I/O OD PWR GND 1 0 X ID H L PD Z VO VI PE Tri N/C Input pin only Output pin only Pin can be either an input or output Open Drain pin Power pin Ground pin Driven to Vcc Driven to Vss Driven to unknown state Input is disabled Pulled up to Vcc Pulled to Vss Pull-up Disabled Output Disabled A valid output level is driven, allowed states -- 1, 0, H, Z Need to drive a valid input level, allowed states - 1, 0, H, Z Pull-up Enabled, equivalent to H Output Only/Tristatable No Connect Pin must be connected as described Description
Table 5.
Other tables in this section include:
* Table 6 -- SDRAM Interface signals * Table 7 -- PCI Controller signals
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
* * * * * * * * * * * *
Table 6.
Table 8 -- High-Speed, Serial Interface 0 signals Table 9 -- High-Speed, Serial Interface 1 signals Table 10 -- MII Interfaces signals Table 11 -- UTOPIA-2 Interface signals Table 12 -- Expansion Bus Interface signals Table 13 -- UART Interfaces signals Table 14 -- USB Interface signals Table 15 -- Oscillator Interface signals Table 16 -- GPIO Interface signals Table 17 -- JTAG Interface signals Table 18 -- System Interface signals Table 19 -- Power Interface signals
SDRAM Interface (Sheet 1 of 2)
Name Power on Reset1 Z Reset2 Type Description SDRAM Address: A0-A12 signals are output during the READ/WRITE commands and ACTIVE commands to select a location in memory to act upon. SDRAM Data: Bidirectional data bus used to transfer data to and from the SDRAM SDRAM Clock: All SDRAM input signals are sampled on the rising edge of SDM_CLKOUT. All output signals are driven with respect to the rising edge of SDM_CLKOUT. SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the bank the current command is attempting to access. SDRAM Row Address strobe/select (active low): Along with SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals determines the current command to be executed. SDRAM Column Address strobe/select (active low): Along with SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals determines the current command to be executed. SDRAM Chip select (active low): CS# enables the command decoder in the external SDRAM when logic low and disables the command decoder in the external SDRAM when logic high. SDRAM Write enable (active low): Along with SDM_CAS_N, SDM_RAS_N, and SDM_CS_N signals determines the current command to be executed.
SDM_ADDR[12:0]
0
O
SDM_DATA[31:0]
Z
1
I/O
SDM_CLKOUT
Z
0
O
SDM_BA[1:0]
Z
0
O
SDM_RAS_N
Z
1
O
SDM_CAS_N
Z
1
O
SDM_CS_N[1:0]
Z
1
O
SDM_WE_N 1. 2.
Z
1
O
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
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Table 6.
SDRAM Interface (Sheet 2 of 2)
Name Power on Reset1 Z Reset2 Type Description SDRAM Clock Enable: CKE is driving high to activate the clock to an external SDRAM and driven low to de-activate the CLK to an external SDRAM. SDRAM Data bus mask: DQM is used to byte select data during read/write access to an external SDRAM.
SDM_CKE
1
O
SDM_DQM[3:0] 1. 2.
Z
0
O
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 7.
PCI Controller (Sheet 1 of 2)
Name Power on Reset2 Type Reset1 Description PCI Address/Data bus used to transfer address and bidirectional data to and from multiple PCI devices. Should be pulled low with a 10-K resistor when not being utilized in the system. PCI Command/Byte Enables is used as a command word during PCI address cycles and as byte enables for data cycles. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI Parity used to check parity across the 32 bits of PCI_AD and the four bits of PCI_CBE_N. Should be pulled low with a 10-K resistor when not being utilized in the system. PCI Cycle Frame used to signify the beginning and duration of a transaction. The signal will be inactive prior to or during the final data phase of a given transaction. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI_TRDY_N Z Z I/O PCI Target Ready informs that the target of the PCI bus is ready to complete the current data phase of a given transaction. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI Initiator Ready informs the PCI bus that the initiator is ready to complete the transaction. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI Stop indicates that the current target is requesting the current initiator to stop the current transaction. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI Parity Error asserted when a PCI parity error is detected -- between the PCI_PAR and associated information on the PCI_AD bus and PCI_CBE_N -- during all PCI transactions, except for Special Cycles. The agent receiving data will drive this signal. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI System Error asserted when a parity error occurs on special cycles or any other error that will cause the PCI bus not to function properly. This signal can function as an input or an open drain output. Should be pulled high with a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
PCI_AD[31:0]
Z
Z
I/O
PCI_CBE_N[3:0]
Z
Z
I/O
PCI_PAR
Z
Z
I/O
PCI_FRAME_N
Z
Z
I/O
PCI_IRDY_N
Z
Z
I/O
PCI_STOP_N
Z
Z
I/O
PCI_PERR_N
Z
Z
I/O
PCI_SERR_N
Z
Z
I/OD
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Table 7.
PCI Controller (Sheet 2 of 2)
Name Power on Reset2 Type Reset1 PCI Device Select: * When used as an output, PCI_DEVSEL_N indicates that device has decoded that address as the target of the requested transaction. * When used as an input, PCI_DEVSEL_N indicates if any device on the PCI bus exists with the given address. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI_IDSEL Z Z I PCI Initialization Device Select is a chip select during configuration reads and writes. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI arbitration request: Used by the internal PCI arbiter to allow an agent to request the PCI bus. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI arbitration request: * When configured as an input (PCI arbiter enabled), the internal PCI arbiter will allow an agent to request the PCI bus. PCI_REQ_N[0] Z Z I/O * When configured as an output (PCI arbiter disabled), the pin will be used to request access to the PCI bus from an external arbiter. Should be pulled high with a 10-K resistor, when the PCI bus is not being utilized in the system. PCI_GNT_N[3:1] Z Z O PCI arbitration grant: Generated by the internal PCI arbiter to allow an agent to claim control of the PCI bus. PCI arbitration grant: * When configured as an output (PCI arbiter enabled), the internal PCI arbiter to allow an agent to claim control of the PCI bus. PCI_GNT_N[0] Z Z I/O * When configured as an input (PCI arbiter disabled), the pin will be used to claim access of the PCI bus from an external arbiter. Should be pulled high with a 10-K resistor when not being utilized in the system. PCI interrupt: Used to request an interrupt. PCI_INTA_N Z Z O/D Should be pulled high with a 10-K resistor when not being utilized in the system. PCI Clock: provides timing for all transactions on PCI. All PCI signals -- except INTA#, INTB#, INTC#, and INTD# -- are sampled on the rising edge of CLK and timing parameters are defined with respect to this edge. The PCI clock rate can operate at up to 66 MHz. Should be pulled low with a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33. Description
PCI_DEVSEL_N
Z
Z
I/O
PCI_REQ_N[3:1]
Z
Z
I
PCI_CLKIN
Z
VI
I
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 8.
High-Speed, Serial Interface 0
Name Power On Reset1 Reset2 Type Description The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to allow an external source become synchronized with the transmitted data. Often known as a Frame Sync signal. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. HSS_TXDATA0 Z Z O/D Transmit data out. Open Drain output. Must be pulled high with a 10-K resistor to VCCP. The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output. The clock can be a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the transmitted data. Configured as an input upon reset. Frame sync and data can be selected to be generated on the rising or falling edge of the transmit clock. Should be pulled low with a 10-K resistor when not being utilized in the system. The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to allow an external source to become synchronized with the received data. Often known as a Frame Sync signal. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. Receive data input. Can be sampled on the rising or falling edge of the receive clock. Should be pulled low through a 10-K resistor when not being utilized in the system. The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
HSS_TXFRAME0
Z
Z
I/O
HSS_TXCLK0
Z
Z
I/O
HSS_RXFRAME0
Z
Z
I/O
HSS_RXDATA0
Z
VI
I
HSS_RXCLK0
Z
Z
I/O
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 9.
High-Speed, Serial Interface 1
Name Power On Reset1 Reset2 Type Description The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized with the transmitted data. Often known as a Frame Sync signal. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. HSS_TXDATA1 Z Z O/D Transmit data out. Open Drain output. Must be pulled high with a 10-K resistor to VCCP. The High-Speed Serial (HSS) transmit clock signal can be configured as an input or an output. The clock can be a frequency ranging from 512 KHz to 8.192 MHz. Used to clock out the transmitted data. Configured as an input upon reset. Frame sync and Data can be selected to be generated on the rising or falling edge of the transmit clock. Should be pulled low with a 10-K resistor when not being utilized in the system. The High-Speed Serial (HSS) receive frame signal can be configured as an input or an output to allow an external source to be synchronized with the received data. Often known as a Frame Sync signal. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. Receive data input. Can be sampled on the rising or falling edge of the receive clock. Should be pulled low through a 10-K resistor when not being utilized in the system. The High-Speed Serial (HSS) receive clock signal can be configured as an input or an output. The clock can be from 512 KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset. Should be pulled low with a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
HSS_TXFRAME1
Z
Z
I/O
HSS_TXCLK1
Z
Z
I/O
HSS_RXFRAME1
Z
Z
I/O
HSS_RXDATA1
Z
VI
I
HSS_RXCLK1
Z
Z
I/O
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 10.
MII Interfaces (Sheet 1 of 2)
Name Power On Reset1 Reset2 Type Description Externally supplied transmit clock. * 25 MHz for 100 Mbps operation ETH_TXCLK0 Z VI I * 2.5 MHz for 10 Mbps Should be pulled low through a 10-K resistor when not being utilized in the system. ETH_TXDATA0[3:0] Z 0 O Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK0. Indicates that the PHY is being presented with nibbles on the MII interface. Asserted synchronously, with respect to ETH_TXCLK0, at the first nibble of the preamble and remains asserted until all the nibbles of a frame are presented. Externally supplied receive clock. * 25 MHz for 100 Mbps operation ETH_RXCLK0 Z VI I * 2.5 MHz for 10 Mbps Should be pulled low through a 10-K resistor when not being utilized in the system. Receive data bus from PHY, data sampled synchronously with respect to ETH_RXCLK0 * Should be pulled low through a 10-K resistor when not being utilized in the system. Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. Should be pulled low through a 10-K resistor when not being utilized in the system. Asserted by the PHY when a collision is detected by the PHY. Should be pulled low through a 10-K resistor when not being utilized in the system. Asserted by the PHY when the transmit medium or receive medium is active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of a collision condition. PHY asserts CRS asynchronously and de-asserts synchronously, with respect to ETH_RXCLK0. Should be pulled low through a 10-K resistor when not being utilized in the system. Management data output. Provides the write data to both PHY devices connected to each MII interface. An external 1.5-K pull-up resistor is required. ETH_MDIO Z Z I/O
Note: If interfacing with a single Intel(R) LXT972 Fast Ethernet Transceiver, and a 1.5K pull-up resistor is not used, the NPE will `see' 32 PHYs on the MII interface.
ETH_TXEN0
Z
0
O
ETH_RXDATA0[3:0]
Z
VI
I
ETH_RXDV0
Z
VI
I
ETH_COL0
Z
VI
I
ETH_CRS0
Z
VI
I
Should be pulled low through a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
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Table 10.
MII Interfaces (Sheet 2 of 2)
Name Power On Reset1 Reset2 Type Description Management data clock. Management data interface clock is used to clock the MDIO signal as an output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be configured to be an output through an Intel API as documented in the Intel(R) IXP400 Software Programmer's Guide. Externally supplied transmit clock. * 25 MHz for 100 Mbps operation ETH_TXCLK1 Z VI I * 2.5 MHz for 10 Mbps Should be pulled low through a 10-K resistor when not being utilized in the system. ETH_TXDATA1[3:0] Z 0 O Transmit data bus to PHY, asserted synchronously with respect to ETH_TXCLK1. Indicates that the PHY is being presented with nibbles on the MII interface. Asserted synchronously, with respect to ETH_TXCLK1, at the first nibble of the preamble, and remains asserted until all the nibbles of a frame are presented. Externally supplied receive clock. * 25 MHz for 100 Mbps operation ETH_RXCLK1 Z VI I * 2.5 MHz for 10 Mbps Should be pulled low through a 10-K resistor when not being utilized in the system. Receive data bus from PHY, data sampled synchronously, with respect to ETH_RXCLK1. * Should be pulled low through a 10-K resistor when not being utilized in the system. Receive data valid, used to inform the MII interface that the Ethernet PHY is sending data. Should be pulled low through a 10-K resistor when not being utilized in the system. Asserted by the PHY when a collision is detected by the PHY. * Should be pulled low through a 10-K resistor when not being utilized in the system. Asserted by the PHY when the transmit medium or receive medium are active. De-asserted when both the transmit and receive medium are idle. Remains asserted throughout the duration of collision condition. PHY asserts CRS asynchronously and de-asserts synchronously with respect to ETH_RXCLK1. Should be pulled low through a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
ETH_MDC
Z
Z
O
ETH_TXEN1
Z
0
O
ETH_RXDATA1[3:0]
Z
VI
I
ETH_RXDV1
Z
VI
I
ETH_COL1
Z
VI
I
ETH_CRS1
Z
VI
I
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Table 11.
UTOPIA-2 Interface (Sheet 1 of 2)
Name Power On Reset1 Reset2 Type Description UTOPIA Transmit clock input. Also known as UTP_TX_CLK. This signal is used to synchronize all UTOPIA-transmit outputs to the rising edge of the UTP_OP_CLK. This signal should be pulled low through a 10-K resistor when not being utilized in the system. UTOPIA flow control output signal. Also known as the TXENB_N signal. Used to inform the selected PHY that data is being transmitted to the PHY. Placing the PHY's address on the UTP_OP_ADDR -- and bringing UTP_OP_FCO to logic 1, during the current clock -- followed by the UTP_OP_FCO going to a logic 0, on the next clock cycle, selects which PHY is active in MPHY mode. In SPHY configurations, UTP_OP_FCO is used to inform the PHY that the processor is ready to send data. Start of Cell. Also known as TX_SOC. UTP_OP_SOC Z Z O Active high signal is asserted when UTP_OP_DATA contains the first valid byte of a transmitted cell. UTOPIA output data. Also known as UTP_TX_DATA. Used to send data from the processor to an ATM UTOPIALevel-2-compliant PHY. Transmit PHY address bus. Used by the processor when operating in MPHY mode to poll and select a single PHY at any given time. UTOPIA Output data flow control input: Also known as the TXFULL/CLAV signal. Used to inform the processor of the ability of each polled PHY to receive a complete cell. For cell-level flow control in an MPHY environment, TxClav is an active high tristateable signal from the MPHY to ATM layer. The UTP_OP_FCI, which is connected to multiple MPHY devices, will see logic high generated by the PHY, one clock after the given PHY address is asserted -- when a full cell can be received by the PHY. The UTP_OP_FCI will see a logic low generated by the PHY one clock cycle, after the PHY address is asserted -- if a full cell cannot be received by the PHY. This signal should be tied low through a 10-K resistor if not being used. UTOPIA Receive clock input. Also known as UTP_RX_CLK. UTP_IP_CLK Z VI I This signal is used to synchronize all UTOPIA-received inputs to the rising edge of the UTP_IP_CLK. This signal should be pulled low through a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
UTP_OP_CLK
Z
VI
I
UTP_OP_FCO
Z
Z
O
UTP_OP_DATA[7:0]
Z
Z
O
UTP_OP_ADDR[4:0]
Z
VI
O
UTP_OP_FCI
Z
VI
I
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 11.
UTOPIA-2 Interface (Sheet 2 of 2)
Name Power On Reset1 Reset2 Type Description UTOPIA Input Data flow control input signal. Also known as RXEMPTY/CLAV. Used to inform the processor of the ability of each polled PHY to send a complete cell. For cell-level flow control in an MPHY environment, RxClav is an active high tristateable signal from the MPHY to ATM layer. The UTP_IP_FCI, which is connected to multiple MPHY devices, will see logic high generated by the PHY, one clock after the given PHY address is asserted, when a full cell can be received by the PHY. The UTP_IP_FCI will see a logic low generated by the PHY, one clock cycle after the PHY address is asserted if a full cell cannot be received by the PHY. In SPHY mode, this signal is used to indicate to the processor that the PHY has an octet or cell available to be transferred to the processor. Should be pulled low through a 10-K resistor when not being utilized in the system. Start of Cell. RX_SOC UTP_IP_SOC Z VI I Active-high signal that is asserted when UTP_IP_DATA contains the first valid byte of a transmitted cell. Should be pulled low through a 10-K resistor when not being utilized in the system. UTOPIA input data. Also known as RX_DATA. UTP_IP_DATA[7:0] Z VI I Used by to the processor to receive data from an ATM UTOPIA-Level-2-compliant PHY. Should be pulled low through a 10-K resistor when not being utilized in the system. Receive PHY address bus. UTP_IP_ADDR[4:0] Z VI O Used by the processor when operating in MPHY mode to poll and select a single PHY at any one given time. UTOPIA Input Data Flow Control Output signal: Also known as the RX_ENB_N. In SPHY configurations, UTP_IP_FCO is used to inform the PHY that the processor is ready to accept data. UTP_IP_FCO Z Z O In MPHY configurations, UTP_IP_FCO is used to select which PHY will drive the UTP_RX_DATA and UTP_RX_SOC signals. The PHY is selected by placing the PHY's address on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1 during the current clock, followed by the UTP_OP_FCO going to a logic 0 on the next clock cycle.
UTP_IP_FCI
Z
VI
I
1. 2.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 12.
Expansion Bus Interface
Name Power On Reset1 Z Reset2 Type Description Input clock signal used to sample all expansion interface inputs and clock all expansion interface outputs. Address-latch enable used for multiplexed address/data bus accesses. Used in Intel and Motorola* multiplexed modes of operation. Expansion-bus address used as an output for data accesses over the expansion bus. Also, used as an input during reset to capture device configuration. These signals have a weak pullup resistor attached internally. Based on the desired configuration, various address signals must be tied low in order for the device to operate in the desired mode. Intel-mode write strobe / Motorola-mode data strobe (EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N). Intel-mode read strobe / Motorola-mode read-not-write (EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N). External chip selects for expansion bus. EX_CS_N[7:0] Z 1 O * Chip selects 0 through 7 can be configured to support Intel or Motorola bus cycles. * Chip selects 4 through 7 can be configured to support TI HPI bus cycles. EX_DATA[15:0] Z 0 I/O Expansion-bus, bidirectional data Data ready/acknowledge from expansion-bus devices. Expansion-bus access is halted when an external device sets EX_IOWAIT_N to logic 0 and resume from the halted location once the external device sets EX_IOWAIT_N to logic 1. This signal affects accesses that use EX_CS_N[7:0] when the chip select is configured in Intel- or Motorola-mode of operation. Should be pulled high through a 10-K resistor when not being utilized in the system. HPI interface ready signals. Can be configured to be active high or active low. These signals are used to halt accesses using Chip Selects 7 through 4 when the chip selects are configured to operate in HPI mode. There is one RDY signal per chip select. This signal only affects accesses that use EX_CS_N[7:4]. Should be pulled low though a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
EX_CLK
Z
I
EX_ALE
Z
0
O
EX_ADDR[23:0]
H
H
I/O
EX_WR_N EX_RD_N
Z Z
1 1
O O
EX_IOWAIT_N
H
H
I
EX_RDY[3:0]
H
H
I
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 13.
UART Interfaces
Name Power On Reset1 Reset2 Type Description UART serial data input to High-Speed UART Pins. RXDATA0 Z VI I Should be pulled low through a 10-K resistor when not being utilized in the system. UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a reset operation. High-Speed Serial UART Pins. UART CLEAR-TO-SEND input to High-Speed UART Pins. When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor. Should be pulled high through a 10-K resistor when not being utilized in the system. UART REQUEST-TO-SEND output: RTS0_N H VO/PE O When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1. LOOP-mode operation holds this signal in its inactive state (logic 1). High-Speed UART Pins. UART serial data input. RXDATA1 Z VI I Should be pulled low through a 10-K resistor when not being utilized in the system. UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a Reset operation. Console UART Pins. UART CLEAR-TO-SEND input to Console UART pins. When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor. Should be pulled high through a 10-K resistor when not being utilized in the system. UART REQUEST-TO-SEND output: RTS1_N H VO/PE O When logic 0, this informs the modem or the data set connected to the UART interface of the processor that the UART is ready to exchange data. A reset sets the request to send signal to logic 1. LOOP-mode operation holds this signal in its inactive state (logic 1). Console UART Pins. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
TXDATA0
Z
VO
O
CTS0_N
H
VI/PE
I
TXDATA1
Z
VO
O
CTS1_N
H
VI/PE
I
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 14.
USB Interface
Name USB_DPOS USB_DNEG 1. 2. Power On Reset1 Z Z Reset2 Z Z Type I/O I/O Description Positive signal of the differential USB receiver/driver. Negative signal of the differential USB receiver/driver.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
Table 15.
Oscillator Interface
Name Power On Reset1 Reset2 Type Description 33.33 MHz, sinusoidal crystal input signal. Can be driven by an oscillator. 33.33 MHz, sinusoidal crystal output signal. Left disconnected when being driven by an oscillator.
OSC_IN OSC_OUT 1. 2.
I O
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
Table 16.
GPIO Interface (Sheet 1 of 2)
Name Power On Reset1 Reset2 Type Description General purpose Input/Output pins. May be configured as an input or an output. As an input, each signal may be configured a processor interrupt. Default after reset is to be configured as inputs. Should be pulled low using a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
GPIO[12:0]
Z
Z
I/O
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 16.
GPIO Interface (Sheet 2 of 2)
Name Power On Reset1 Reset2 Type Description General purpose input/output pins. May be configured as an input or an output. Default after reset is to be configured as inputs. Should be pulled low using a 10-K resistor when not being utilized in the system. Can be configured similar to GPIO Pin 13 or as a clock output. Configuration as an output clock can be set at various speeds of up to 33.33 MHz with various duty cycles. Configured as an input, upon reset. Should be pulled low though a 10-K resistor when not being utilized in the system. Can be configured similar to GPIO Pin 13 or as a clock output. Configuration as an output clock can be set at various speeds of up to 33.33 MHz with various duty cycles. Configured as an output, upon reset. Can be used to clock the expansion interface, after reset. Should be pulled low though a 10-K resistor when not being utilized in the system. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
GPIO[13]
Z
Z
I/O
GPIO[14]
Z
Z
I/O
GPIO[15]
Z
CLKOU T/VO
I/O
Table 17.
JTAG Interface
Name JTG_TMS JTG_TDI JTG_TDO Power On Reset1 H H Z Reset2 VI/PE VI/PE VO Type I I O Description Test mode select for the IEEE 1149.1 JTAG interface. Input data for the IEEE 1149.1 JTAG interface. Output data for the IEEE 1149.1 JTAG interface. Used to reset the IEEE 1149.1 JTAG interface. JTG_TRST_N H VI/PE I The JTG_TRST_N signal must be asserted (driven low) during power-up, otherwise the TAP controller may not be initialized properly, and the processor may be locked. When the JTAG interface is not being used, the signal must be pulled low using a 10-K resistor. JTG_TCK 1. 2. Z VI I Used as the clock for the IEEE 1149.1 JTAG interface.
While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 18.
System Interface
Name Power On Reset1 Z H Reset2 Type Description Used for test purposes only. Must be pulled high for normal operation. Used for test purposes only. Must be pulled high for normal operation. Used as a reset input to the device after power up conditions have been met. Power up conditions include the power supplies reaching a safe stable condition and the PLL achieving a locked state and the PWRON_RESET_N coming to an active state prior to the RESET_IN_N coming to an active state. Signal used at power up to reset all internal logic to a known state after the PLL has achieved a locked state. The PWRON_RESET_N input is a 1.3-V tolerant only. Used for test purposes only. Must be pulled high for normal operation. Signal used to inform external reset logic that the internal PLL has achieved a locked state. Signal used to control PCI drive strength characteristics. Drive strength is varied on PCI address, data and control signals. Pin requires a 34- +/- 1% tolerance resistor to ground. Refer to Figure 13 on page 85. 1. 2. While PWRON_RESET_N is deasserted use Power On Reset column for the pin state. After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of PLL_LOCK, all signals reflect the value shown in the RESET column. For a legend of the Type codes, see Table 5 on page 33. IMPORTANT NOTE: When a system-level reset is asserted to the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor -- either via a power-on reset, a system reset, or a Watchdog-Timer reset -- and any interface is in an active transaction (particularly the PCI bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a reset of other attached devices may be required.
BYPASS_CLK SCANTESTMODE_N
VI VI/PE
I I
RESET_IN_N
0
VI
I
PWRON_RESET_N
0
VI
I
HIGHZ_N PLL_LOCK
H Z
VI/PE VO
I O
RCOMP
I
Table 19.
Power Interface (Sheet 1 of 2)
Name VCC VCCP VSS VCCOSCP I Type I I Description 1.3-V power supply input pins used for the internal logic. 3.3-V power supply input pins used for the peripheral (I/O) logic. Ground power supply input pins used for both the 3.3-V and the 1.3-V power supplies. 3.3-V power supply input pins used for the peripheral (I/O) logic of the analog oscillator circuitry. Require special power filtering circuitry. Refer to Figure 11 on page 84 VSSOSCP I Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry. Used in conjunction with the VCCOSCP pins. Requires special power filtering circuitry. Refer to Figure 11 on page 84 For a legend of the Type codes, see Table 5 on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 19.
Power Interface (Sheet 2 of 2)
Name Type Description 1.3-V power supply input pins used for the internal logic of the analog oscillator circuitry. Requires special power filtering circuitry. Refer to Figure 12 on page 84 VSSOSC I Ground power supply input pins used for the internal logic of the analog oscillator circuitry. Used in conjunction with the VCCOSC pins. Requires special power filtering circuitry. Refer to Figure 12 on page 84 VCCPLL1 I 1.3-V power supply input pins used for the internal logic of the analog phase lock-loop circuitry. Requires special power filtering circuitry. Refer to Figure 9 on page 83 VCCPLL2 I 1.3-V power supply input pins used for the internal logic of the analog phase lock-loop circuitry. Requires special power filtering circuitry. Refer to Figure 10 on page 83 For a legend of the Type codes, see Table 5 on page 33.
VCCOSC
I
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
4.0
Package and Pinout Information
The Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial-temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for extended-temperature applications.
4.1
Figure 7.
Package Description
492-Pin Lead PBGA Package
-A0.127 A
35.00 0.20 30.00 0.25
2
-B-
(1)
o 0.90 0.60
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
Pin #1 Corner
o 0.30
S CAS BS
Pin 1 ID 35.00 0.20 22.00 REF 30.00 0.25
1.27
+ +
(2)
1.63 REF
+
++
45 Chamfer 4 Places
22.00 REF
o1.0 3 Places
1.63 REF
1.27
TOP VIEW
2.38 0.21 1.17 0.05
30
0.15 0.20
C -C-
0.61 0.06 0.60 0.10
3
Seating Plane
SIDE VIEW
B1268-03
1. 2. 3.
All measurements are in millimeters (mm). The size of the land pad at the interposer side (1) is 0.81 mm. The size of the solder resist at the interposer side (2) is 0.66 mm.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 8.
Package Markings
Pin #1
(Not a mark)
i
FWIXP42 XBX INTEL M C 2002
Level 1 Name
*
BSMC marking zone: 0.380" max.
YWW KOREA
BSMC (ATPO#, Date Code and COO)
Note:
See Table 20 for specific on "Level 1 Name."
Table 20.
Part Numbers (Sheet 1 of 2)
Device Intel(R) IXP425 Network Processor Intel(R) IXP425 Network Processor Intel(R) IXP425 Network Processor Intel(R) IXP425 Network Processor Intel(R) IXP425 Network Processor Intel(R) IXP425 Network Processor Intel(R) IXP423 Network Processor Intel(R) IXP422 Network Processor Intel(R) IXP421 Network Processor Stepping Speed (MHz) 533 Part #
B-0
FWIXP425BD
B-0
400
FWIXP425BC
B-0
266 533 Extended Temperature 400 Extended Temperature 266 Extended Temperature 266
FWIXP425BB
B-0
GWIXP425BDT
B-0
GWIXP425BCT
B-0
GWIXP425BBT
B-0
FWIXP423BB
B-0
266
FWIXP422BB
B-0
266
FWIXP421BB
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 20.
Part Numbers (Sheet 2 of 2)
Device Intel(R) IXP420 Network Processor Intel(R) IXP420 Network Processor Intel(R) IXP420 Network Processor Intel(R) IXP420 Network Processor Intel(R) IXC1100 Control Plane Processor Intel(R) IXC1100 Control Plane Processor Intel(R) IXC1100 Control Plane Processor Intel(R) IXC1100 Control Plane Processor Intel(R) IXC1100 Control Plane Processor Intel(R) IXC1100 Control Plane Processor Stepping Speed (MHz) 533 Part #
B-0
FWIXP420BD
B-0
400
FWIXP420BC
B-0
266 266
FWIXP420BB
B-0
Extended Temperature 533
GWIXP420BBT
B-0
FWIXC1100BD
B-0
400
FWIXC1100BC
B-0
266 533 Extended Temperature 400 Extended Temperature 266 Extended Temperature
FWIXC1100BB
B-0
GWIXC1100BDT
B-0
GWIXC1100BCT
B-0
GWIXC1100BBT
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
4.2
Signal-Pin Descriptions
In this section, separate ball-map-assignment tables are given for each model of the IXP42X product line and IXC1100 control plane processors. These tables include:
Device Intel IXP425 Network Processor Intel IXP423 Network Processor Intel(R) IXP422 Network Processor Intel IXP421 Network Processor Intel IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor
(R) (R) (R) (R)
Table # 21 21 22 23 24
Starting Page 53 53 60 67 74
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 1 of 7)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26
Note:
Signal PCI_AD[27] PCI_GNT_N[1] PCI_GNT_N[3] SDM_DATA[19] SDM_DATA[27] SDM_DATA[26] SDM_DATA[25] SDM_DATA[23] SDM_DATA[14] SDM_DATA[13] SDM_DATA[11] SDM_DATA[10] SDM_DATA[6] SDM_DATA[8] SDM_DQM[1] SDM_CS_N[0] SDM_CLKOUT SDM_RAS_N SDM_ADDR[12] SDM_ADDR[9] SDM_ADDR[8] SDM_ADDR[5] EX_RD_N EX_ADDR[1] EX_ADDR[3] EX_ADDR[5]
Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26
Signal PCI_AD[28] VCCP PCI_GNT_N[2] VCCP SDM_DATA[28] VCCP SDM_DATA[21] VSS SDM_DATA[0] VCCP SDM_DATA[12] VSS SDM_DATA[9] VCCP SDM_DQM[2] VSS SDM_CKE VCCP SDM_ADDR[10] VSS SDM_ADDR[1] VCCP EX_IOWAIT_N VSS VCCP EX_ADDR[9]
Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26
Signal PCI_AD[26] PCI_AD[30] VSS PCI_INTA_N VSS SDM_DATA[18] VSS VCCP SDM_DATA[24] VSS SDM_DATA[2] SDM_DATA[4] VSS SDM_DATA[7] SDM_DQM[3] VCCP SDM_CAS_N SDM_ADDR[11] VSS SDM_ADDR[6] SDM_ADDR[2] VSS EX_ADDR[0] EX_ADDR[4] EX_ADDR[7] EX_ADDR[13]
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
Signal PCI_AD[25] VSS PCI_AD[31] VCC PCI_SERR_N VCC SDM_DATA[29] SDM_DATA[20] VCC SDM_DATA[15] SDM_DATA[1] VCC SDM_DATA[5] VCC SDM_WE_N SDM_CS_N[1] SDM_BA[1] VCC SDM_ADDR[0] VSS VCC EX_ALE VCC EX_ADDR[6] RCOMP EX_ADDR[17]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 2 of 7)
Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26
Note:
Signal PCI_AD[23] VCCP PCI_REQ_N[2] VSS PCI_GNT_N[0] SDM_DATA[16] VCCP SDM_DATA[30] VSS SDM_DATA[22] VCCP SDM_DATA[3] VSS SDM_DQM[0] VCCP SDM_BA[0] VSS SDM_ADDR[7] VCCP SDM_ADDR[3] USB_DNEG VCCP VSS EX_ADDR[10] EX_ADDR[15] EX_ADDR[19]
Ball F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Signal PCI_AD[20] PCI_IDSEL VCC PCI_REQ_N[0] VCCP VCC SDM_DATA[31] VSS SDM_DATA[17] VCC
Ball G1 G2 G3 G4 G5 G6
Signal PCI_AD[21] VCCP PCI_AD[24] VSS PCI_REQ_N[1] VSS
Ball H1 H2 H3 H4 H5 H6
Signal PCI_AD[16] PCI_AD[18] VCC PCI_CBE_N[3] VCC PCI_REQ_N[3]
F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
VCC SDM_ADDR[4] VSS USB_DPOS VCC EX_WR_N VCC EX_ADDR[14] VCCP EX_ADDR[21] G21 G22 G23 G24 G25 G26 EX_ADDR[2] VSS EX_ADDR[12] VSS EX_ADDR[20] EX_ADDR[22] H21 H22 H23 H24 H25 H26 VSS EX_ADDR[11] EX_ADDR[18] VCCP VSS EX_CS_N[1]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 3 of 7)
Ball J1 J2 J3 J4 J5 J6 Signal PCI_CLKIN VCCP VSS PCI_AD[22] VSS PCI_AD[29] Ball K1 K2 K3 K4 K5 K6 Signal PCI_CBE_N[2] VSS PCI_AD[17] VCCP PCI_AD[19] VCC Ball L1 L2 L3 L4 L5 Signal PCI_DEVSEL_N VCCP PCI_STOP_N VCC PCI_FRAME_N Ball M1 M2 M3 M4 M5 Signal PCI_CBE_N[1] PCI_PAR VSS PCI_IRDY_N VCCP
L11 L12 L13 L14 L15 L16
VSS VSS VSS VSS VSS VSS
M11 M12 M13 M14 M15 M16
VSS VSS VSS VSS VSS VSS
J21 J22 J23 J24 J25 J26
Note:
EX_ADDR[8] EX_ADDR[16] VCC EX_ADDR[23] EX_CS_N[2] EX_CS_N[4]
K21 K22 K23 K24 K25 K26
VCC VSS EX_CS_N[0] EX_CS_N[3] VCCP EX_CS_N[7] L22 L23 L24 L25 L26 VCCP VCC EX_CS_N[6] EX_DATA[0] EX_DATA[1] M22 M23 M24 M25 M26 EX_CS_N[5] EX_CLK EX_DATA[2] VSS EX_DATA[3]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 4 of 7)
Ball N1 N2 N3 N4 N5 Signal PCI_AD[11] VCCP VCC PCI_PERR_N PCI_AD[15] Ball P1 P2 P3 P4 P5 Signal PCI_CBE_N[0] PCI_AD[14] PCI_AD[13] VSS PCI_AD[12] Ball R1 R2 R3 R4 R5 Signal PCI_AD[10] VSS PCI_AD[9] VCC PCI_AD[4] Ball T1 T2 T3 T4 T5 Signal PCI_AD[6] PCI_TRDY_N VSS PCI_AD[2] VCCP
N11 N12 N13 N14 N15 N16
VSS VSS VSS VSS VSS VSS
P11 P12 P13 P14 P15 P16
VSS VSS VSS VSS VSS VSS
R11 R12 R13 R14 R15 R16
VSS VSS VSS VSS VSS VSS
T11 T12 T13 T14 T15 T16
VSS VSS VSS VSS VSS VSS
N22 N23 N24 N25 N26
Note:
VCC VSS VCC EX_DATA[4] EX_DATA[5]
P22 P23 P24 P25 P26
EX_DATA[6] EX_DATA[7] EX_DATA[8] VCCP EX_DATA[9]
R22 R23 R24 R25 R26
VCCP VCC EX_DATA[12] EX_DATA[11] EX_DATA[10]
T22 T23 T24 T25 T26
EX_RDY_N[0] VSS EX_DATA[14] VSS EX_DATA[13]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 5 of 7)
Ball U1 U2 U3 U4 U5 U6 Signal PCI_AD[8] VCCP PCI_AD[0] PCI_AD[7] HSS_TXDATA0 VCC Ball V1 V2 V3 V4 V5 V6 Signal PCI_AD[5] VSS PCI_AD[3] VCC HSS_TXFRAME0 VSS Ball W1 W2 W3 W4 W5 W6 Signal PCI_AD[1] VCCP HSS_RXFRAME0 VSS HSS_TXCLK1 HSS_RXFRAME1 Ball Y1 Y2 Y3 Y4 Y5 Y6 Signal HSS_TXCLK0 HSS_RXCLK0 HSS_TXFRAME1 VCC VCCP ETH_TXEN0
U21 U22 U23 U24 U25 U26
Note:
VCC GPIO[14] EX_RDY_N[1] EX_RDY_N[2] GPIO[15] EX_DATA[15]
V21 V22 V23 V24 V25 V26
GPIO[6] GPIO[9] VCC GPIO[13] VCCP EX_RDY_N[3]
W21 W22 W23 W24 W25 W26
GPIO[1] VCCP GPIO[8] VSS GPIO[11] GPIO[12]
Y21 Y22 Y23 Y24 Y25 Y26
RXDATA1 GPIO[0] VCC GPIO[5] VCCP GPIO[10]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
March 2005 57
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 6 of 7)
Ball AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 Signal HSS_RXDATA0 VCCP VSS HSS_RXCLK1 ETH_TXDATA0[2] VCC ETH_RXDATA0[1] VSS ETH_TXDATA1[1] VCC Ball AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AA17 AA18 AA20 AA21 AA22 AA23 AA24 AA25 AA26
Note:
Signal HSS_TXDATA1 HSS_RXDATA1 ETH_TXDATA0[3] ETH_TXDATA0[1] VSS ETH_RXCLK0 VCCP ETH_TXDATA1[2] ETH_RXDATA1[1] VCCP VCCP VSS UTP_OP_DATA[7] VCCP UTP_OP_SOC VSS UTP_IP_DATA[6] VCCP UTP_IP_CLK UTP_IP_ADDR[1] VCCP CTS0_N CTS1_N VCCP GPIO[4]
Ball AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC16 AC18 AC19 AC20 AC22 AC23 AC24 AC25 AC26
Signal VSS ETH_TXDATA0[0] VCCP VCC ETH_RXDATA0[0] VSS VCC ETH_RXDATA1[2] VCC VCC VCCOSCP VCC RESET_IN_N VCC UTP_OP_FCI VCC UTP_IP_DATA[2] UTP_IP_SOC VCC JTG_TRST_N VCC RXDATA0 RTS1_N GPIO[2]
Ball AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD14 AD16 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26
Signal ETH_TXCLK0 ETH_RXDV0 VSS ETH_CRS0 ETH_MDC ETH_TXDATA1[0] ETH_RXDATA1[3] ETH_RXCLK1 VSS VSSOSCP VCCP PLL_LOCK UTP_OP_DATA[4] UTP_OP_DATA[2] VSS UTP_OP_ADDR[3] UTP_IP_DATA[7] VCCP UTP_IP_DATA[1] UTP_IP_ADDR[4] VSS JTG_TDO VSS TXDATA0 RTS0_N
AD13 PWRON_RESET_N
AC15 UTP_OP_DATA[1] AD15 AC17 UTP_OP_ADDR[1] AD17
VCC UTP_IP_FCI VSS VCC TXDATA1 VSS GPIO[3] VSS GPIO[7]
AB17 AB18 AB20 AB22 AB23 AB24 AB25 AB26
AA19 UTP_IP_ADDR[0] AB19
AB21 SCANTESTMODE_N AC21
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 21.
Ball Map Assignment for the Intel(R) IXP425 Network Processor (Sheet 7 of 7)
Ball AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE15 AE16 AE17 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Note:
Signal ETH_RXDATA0[3] VCCP ETH_COL0 ETH_TXEN1 VCCP ETH_RXDV1 VSS ETH_COL1 VCCP VCCPLL1 VSS VCCPLL2 VCCP VSS UTP_OP_FCO VCCP VSS UTP_IP_DATA[4] VCCP UTP_IP_FCO VCCP JTG_TDI VCCP HIGHZ_N
Ball AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF15 AF16 AF17 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal ETH_RXDATA0[2] ETH_MDIO (Reserved) ETH_TXDATA1[3] ETH_TXCLK1 ETH_RXDATA1[0] ETH_CRS1 VSSOSC OSC_IN VSSOSCP OSC_OUT VCCOSC BYPASS_CLK UTP_OP_DATA[6] UTP_OP_DATA[3] UTP_OP_DATA[0] UTP_OP_CLK UTP_OP_ADDR[4] UTP_OP_ADDR[0] UTP_IP_DATA[5] UTP_IP_DATA[3] UTP_IP_DATA[0] UTP_IP_ADDR[3] UTP_IP_ADDR[2] JTG_TMS JTG_TCK
Ball
Signal
Ball
Signal
AE14 UTP_OP_DATA[5] AF14
AE18 UTP_OP_ADDR[2] AF18
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 1 of 7)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26
Note:
Signal PCI_AD[27] PCI_GNT_N[1] PCI_GNT_N[3] SDM_DATA[19] SDM_DATA[27] SDM_DATA[26] SDM_DATA[25] SDM_DATA[23] SDM_DATA[14] SDM_DATA[13] SDM_DATA[11] SDM_DATA[10] SDM_DATA[6] SDM_DATA[8] SDM_DQM[1] SDM_CS_N[0] SDM_CLKOUT SDM_RAS_N SDM_ADDR[12] SDM_ADDR[9] SDM_ADDR[8] SDM_ADDR[5] EX_RD_N EX_ADDR[1] EX_ADDR[3] EX_ADDR[5]
Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26
Signal PCI_AD[28] VCCP PCI_GNT_N[2] VCCP SDM_DATA[28] VCCP SDM_DATA[21] VSS SDM_DATA[0] VCCP SDM_DATA[12] VSS SDM_DATA[9] VCCP SDM_DQM[2] VSS SDM_CKE VCCP SDM_ADDR[10] VSS SDM_ADDR[1] VCCP EX_IOWAIT_N VSS VCCP EX_ADDR[9]
Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26
Signal PCI_AD[26] PCI_AD[30] VSS PCI_INTA_N VSS SDM_DATA[18] VSS VCCP SDM_DATA[24] VSS SDM_DATA[2] SDM_DATA[4] VSS SDM_DATA[7] SDM_DQM[3] VCCP SDM_CAS_N SDM_ADDR[11] VSS SDM_ADDR[6] SDM_ADDR[2] VSS EX_ADDR[0] EX_ADDR[4] EX_ADDR[7] EX_ADDR[13]
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
Signal PCI_AD[25] VSS PCI_AD[31] VCC PCI_SERR_N VCC SDM_DATA[29] SDM_DATA[20] VCC SDM_DATA[15] SDM_DATA[1] VCC SDM_DATA[5] VCC SDM_WE_N SDM_CS_N[1] SDM_BA[1] VCC SDM_ADDR[0] VSS VCC EX_ALE VCC EX_ADDR[6] RCOMP EX_ADDR[17]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 2 of 7)
Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26
Note:
Signal PCI_AD[23] VCCP PCI_REQ_N[2] VSS PCI_GNT_N[0] SDM_DATA[16] VCCP SDM_DATA[30] VSS SDM_DATA[22] VCCP SDM_DATA[3] VSS SDM_DQM[0] VCCP SDM_BA[0] VSS SDM_ADDR[7] VCCP SDM_ADDR[3] USB_DNEG VCCP VSS EX_ADDR[10] EX_ADDR[15] EX_ADDR[19]
Ball F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Signal PCI_AD[20] PCI_IDSEL VCC PCI_REQ_N[0] VCCP VCC SDM_DATA[31] VSS SDM_DATA[17] VCC
Ball G1 G2 G3 G4 G5 G6
Signal PCI_AD[21] VCCP PCI_AD[24] VSS PCI_REQ_N[1] VSS
Ball H1 H2 H3 H4 H5 H6
Signal PCI_AD[16] PCI_AD[18] VCC PCI_CBE_N[3] VCC PCI_REQ_N[3]
F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
VCC SDM_ADDR[4] VSS USB_DPOS VCC EX_WR_N VCC EX_ADDR[14] VCCP EX_ADDR[21] G21 G22 G23 G24 G25 G26 EX_ADDR[2] VSS EX_ADDR[12] VSS EX_ADDR[20] EX_ADDR[22] H21 H22 H23 H24 H25 H26 VSS EX_ADDR[11] EX_ADDR[18] VCCP VSS EX_CS_N[1]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 3 of 7)
Ball J1 J2 J3 J4 J5 J6 Signal PCI_CLKIN VCCP VSS PCI_AD[22] VSS PCI_AD[29] Ball K1 K2 K3 K4 K5 K6 Signal PCI_CBE_N[2] VSS PCI_AD[17] VCCP PCI_AD[19] VCC Ball L1 L2 L3 L4 L5 Signal PCI_DEVSEL_N VCCP PCI_STOP_N VCC PCI_FRAME_N Ball M1 M2 M3 M4 M5 Signal PCI_CBE_N[1] PCI_PAR VSS PCI_IRDY_N VCCP
L11 L12 L13 L14 L15 L16
VSS VSS VSS VSS VSS VSS
M11 M12 M13 M14 M15 M16
VSS VSS VSS VSS VSS VSS
J21 J22 J23 J24 J25 J26
Note:
EX_ADDR[8] EX_ADDR[16] VCC EX_ADDR[23] EX_CS_N[2] EX_CS_N[4]
K21 K22 K23 K24 K25 K26
VCC VSS EX_CS_N[0] EX_CS_N[3] VCCP EX_CS_N[7] L22 L23 L24 L25 L26 VCCP VCC EX_CS_N[6] EX_DATA[0] EX_DATA[1] M22 M23 M24 M25 M26 EX_CS_N[5] EX_CLK EX_DATA[2] VSS EX_DATA[3]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 4 of 7)
Ball N1 N2 N3 N4 N5 Signal PCI_AD[11] VCCP VCC PCI_PERR_N PCI_AD[15] Ball P1 P2 P3 P4 P5 Signal PCI_CBE_N[0] PCI_AD[14] PCI_AD[13] VSS PCI_AD[12] Ball R1 R2 R3 R4 R5 Signal PCI_AD[10] VSS PCI_AD[9] VCC PCI_AD[4] Ball T1 T2 T3 T4 T5 Signal PCI_AD[6] PCI_TRDY_N VSS PCI_AD[2] VCCP
N11 N12 N13 N14 N15 N16
VSS VSS VSS VSS VSS VSS
P11 P12 P13 P14 P15 P16
VSS VSS VSS VSS VSS VSS
R11 R12 R13 R14 R15 R16
VSS VSS VSS VSS VSS VSS
T11 T12 T13 T14 T15 T16
VSS VSS VSS VSS VSS VSS
N22 N23 N24 N25 N26
Note:
VCC VSS VCC EX_DATA[4] EX_DATA[5]
P22 P23 P24 P25 P26
EX_DATA[6] EX_DATA[7] EX_DATA[8] VCCP EX_DATA[9]
R22 R23 R24 R25 R26
VCCP VCC EX_DATA[12] EX_DATA[11] EX_DATA[10]
T22 T23 T24 T25 T26
EX_RDY_N[0] VSS EX_DATA[14] VSS EX_DATA[13]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 5 of 7)
Ball U1 U2 U3 U4 U5 U6 Signal PCI_AD[8] VCCP PCI_AD[0] PCI_AD[7] N/C VCC Ball V1 V2 V3 V4 V5 V6 Signal PCI_AD[5] VSS PCI_AD[3] VCC N/C VSS Ball W1 W2 W3 W4 W5 W6 Signal PCI_AD[1] VCCP N/C VSS N/C N/C Ball Y1 Y2 Y3 Y4 Y5 Y6 Signal N/C N/C N/C VCC VCCP ETH_TXEN0
U21 U22 U23 U24 U25 U26
Note:
VCC GPIO[14] EX_RDY_N[1] EX_RDY_N[2] GPIO[15] EX_DATA[15]
V21 V22 V23 V24 V25 V26
GPIO[6] GPIO[9] VCC GPIO[13] VCCP EX_RDY_N[3]
W21 W22 W23 W24 W25 W26
GPIO[1] VCCP GPIO[8] VSS GPIO[11] GPIO[12]
Y21 Y22 Y23 Y24 Y25 Y26
RXDATA1 GPIO[0] VCC GPIO[5] VCCP GPIO[10]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 6 of 7)
Ball AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 Signal N/C VCCP VSS N/C ETH_TXDATA0[2] VCC ETH_RXDATA0[1] VSS ETH_TXDATA1[1] VCC Ball AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26
Note:
Signal N/C N/C ETH_TXDATA0[3] ETH_TXDATA0[1] VSS ETH_RXCLK0 VCCP ETH_TXDATA1[2] ETH_RXDATA1[1] VCCP VCCP VSS N/C VCCP N/C VSS N/C VCCP N/C N/C VCCP CTS0_N CTS1_N VCCP GPIO[4]
Ball AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC22 AC23 AC24 AC25 AC26
Signal VSS ETH_TXDATA0[0] VCCP VCC ETH_RXDATA0[0] VSS VCC ETH_RXDATA1[2] VCC VCC VCCOSCP VCC RESET_IN_N VCC N/C N/C N/C VCC N/C N/C VCC JTG_TRST_N VCC RXDATA0 RTS1_N GPIO[2]
Ball AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26
Signal ETH_TXCLK0 ETH_RXDV0 VSS ETH_CRS0 ETH_MDC ETH_TXDATA1[0] ETH_RXDATA1[3] ETH_RXCLK1 VSS VSSOSCP VCCP PLL_LOCK N/C N/C VSS N/C N/C VCCP N/C N/C VSS JTG_TDO VSS TXDATA0 RTS0_N
AD13 PWRON_RESET_N
VCC N/C N/C VSS VCC TXDATA1 VSS GPIO[3] VSS GPIO[7]
AB17 AB18 AB19 AB20 AB22 AB23 AB24 AB25 AB26
AB21 SCANTESTMODE_N AC21
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 22.
Ball Map Assignment for the Intel(R) IXP422 Network Processor (Sheet 7 of 7)
Ball AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Note:
Signal ETH_RXDATA0[3] VCCP ETH_COL0 ETH_TXEN1 VCCP ETH_RXDV1 VSS ETH_COL1 VCCP VCCPLL1 VSS VCCPLL2 VCCP N/C VSS N/C VCCP N/C VSS N/C VCCP N/C VCCP JTG_TDI VCCP HIGHZ_N
Ball AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal ETH_RXDATA0[2] ETH_MDIO (Reserved) ETH_TXDATA1[3] ETH_TXCLK1 ETH_RXDATA1[0] ETH_CRS1 VSSOSC OSC_IN VSSOSCP OSC_OUT VCCOSC BYPASS_CLK N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C JTG_TMS JTG_TCK
Ball
Signal
Ball
Signal
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 1 of 7)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26
Note:
Signal PCI_AD[27] PCI_GNT_N[1] PCI_GNT_N[3] SDM_DATA[19] SDM_DATA[27] SDM_DATA[26] SDM_DATA[25] SDM_DATA[23] SDM_DATA[14] SDM_DATA[13] SDM_DATA[11] SDM_DATA[10] SDM_DATA[6] SDM_DATA[8] SDM_DQM[1] SDM_CS_N[0] SDM_CLKOUT SDM_RAS_N SDM_ADDR[12] SDM_ADDR[9] SDM_ADDR[8] SDM_ADDR[5] EX_RD_N EX_ADDR[1] EX_ADDR[3] EX_ADDR[5]
Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26
Signal PCI_AD[28] VCCP PCI_GNT_N[2] VCCP SDM_DATA[28] VCCP SDM_DATA[21] VSS SDM_DATA[0] VCCP SDM_DATA[12] VSS SDM_DATA[9] VCCP SDM_DQM[2] VSS SDM_CKE VCCP SDM_ADDR[10] VSS SDM_ADDR[1] VCCP EX_IOWAIT_N VSS VCCP EX_ADDR[9]
Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26
Signal PCI_AD[26] PCI_AD[30] VSS PCI_INTA_N VSS SDM_DATA[18] VSS VCCP SDM_DATA[24] VSS SDM_DATA[2] SDM_DATA[4] VSS SDM_DATA[7] SDM_DQM[3] VCCP SDM_CAS_N SDM_ADDR[11] VSS SDM_ADDR[6] SDM_ADDR[2] VSS EX_ADDR[0] EX_ADDR[4] EX_ADDR[7] EX_ADDR[13]
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
Signal PCI_AD[25] VSS PCI_AD[31] VCC PCI_SERR_N VCC SDM_DATA[29] SDM_DATA[20] VCC SDM_DATA[15] SDM_DATA[1] VCC SDM_DATA[5] VCC SDM_WE_N SDM_CS_N[1] SDM_BA[1] VCC SDM_ADDR[0] VSS VCC EX_ALE VCC EX_ADDR[6] RCOMP EX_ADDR[17]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 2 of 7)
Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26
Note:
Signal PCI_AD[23] VCCP PCI_REQ_N[2] VSS PCI_GNT_N[0] SDM_DATA[16] VCCP SDM_DATA[30] VSS SDM_DATA[22] VCCP SDM_DATA[3] VSS SDM_DQM[0] VCCP SDM_BA[0] VSS SDM_ADDR[7] VCCP SDM_ADDR[3] USB_DNEG VCCP VSS EX_ADDR[10] EX_ADDR[15] EX_ADDR[19]
Ball F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Signal PCI_AD[20] PCI_IDSEL VCC PCI_REQ_N[0] VCCP VCC SDM_DATA[31] VSS SDM_DATA[17] VCC
Ball G1 G2 G3 G4 G5 G6
Signal PCI_AD[21] VCCP PCI_AD[24] VSS PCI_REQ_N[1] VSS
Ball H1 H2 H3 H4 H5 H6
Signal PCI_AD[16] PCI_AD[18] VCC PCI_CBE_N[3] VCC PCI_REQ_N[3]
F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
VCC SDM_ADDR[4] VSS USB_DPOS VCC EX_WR_N VCC EX_ADDR[14] VCCP EX_ADDR[21] G21 G22 G23 G24 G25 G26 EX_ADDR[2] VSS EX_ADDR[12] VSS EX_ADDR[20] EX_ADDR[22] H21 H22 H23 H24 H25 H26 VSS EX_ADDR[11] EX_ADDR[18] VCCP VSS EX_CS_N[1]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 3 of 7)
Ball J1 J2 J3 J4 J5 J6 Signal PCI_CLKIN VCCP VSS PCI_AD[22] VSS PCI_AD[29] Ball K1 K2 K3 K4 K5 K6 Signal PCI_CBE_N[2] VSS PCI_AD[17] VCCP PCI_AD[19] VCC Ball L1 L2 L3 L4 L5 Signal PCI_DEVSEL_N VCCP PCI_STOP_N VCC PCI_FRAME_N Ball M1 M2 M3 M4 M5 Signal PCI_CBE_N[1] PCI_PAR VSS PCI_IRDY_N VCCP
L11 L12 L13 L14 L15 L16
VSS VSS VSS VSS VSS VSS
M11 M12 M13 M14 M15 M16
VSS VSS VSS VSS VSS VSS
J21 J22 J23 J24 J25 J26
Note:
EX_ADDR[8] EX_ADDR[16] VCC EX_ADDR[23] EX_CS_N[2] EX_CS_N[4]
K21 K22 K23 K24 K25 K26
VCC VSS EX_CS_N[0] EX_CS_N[3] VCCP EX_CS_N[7] L22 L23 L24 L25 L26 VCCP VCC EX_CS_N[6] EX_DATA[0] EX_DATA[1] M22 M23 M24 M25 M26 EX_CS_N[5] EX_CLK EX_DATA[2] VSS EX_DATA[3]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 4 of 7)
Ball N1 N2 N3 N4 N5 Signal PCI_AD[11] VCCP VCC PCI_PERR_N PCI_AD[15] Ball P1 P2 P3 P4 P5 Signal PCI_CBE_N[0] PCI_AD[14] PCI_AD[13] VSS PCI_AD[12] Ball R1 R2 R3 R4 R5 Signal PCI_AD[10] VSS PCI_AD[9] VCC PCI_AD[4] Ball T1 T2 T3 T4 T5 Signal PCI_AD[6] PCI_TRDY_N VSS PCI_AD[2] VCCP
N11 N12 N13 N14 N15 N16
VSS VSS VSS VSS VSS VSS
P11 P12 P13 P14 P15 P16
VSS VSS VSS VSS VSS VSS
R11 R12 R13 R14 R15 R16
VSS VSS VSS VSS VSS VSS
T11 T12 T13 T14 T15 T16
VSS VSS VSS VSS VSS VSS
N22 N23 N24 N25 N26
Note:
VCC VSS VCC EX_DATA[4] EX_DATA[5]
P22 P23 P24 P25 P26
EX_DATA[6] EX_DATA[7] EX_DATA[8] VCCP EX_DATA[9]
R22 R23 R24 R25 R26
VCCP VCC EX_DATA[12] EX_DATA[11] EX_DATA[10]
T22 T23 T24 T25 T26
EX_RDY_N[0] VSS EX_DATA[14] VSS EX_DATA[13]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 5 of 7)
Ball U1 U2 U3 U4 U5 U6 Signal PCI_AD[8] VCCP PCI_AD[0] PCI_AD[7] HSS_TXDATA0 VCC Ball V1 V2 V3 V4 V5 V6 Signal PCI_AD[5] VSS PCI_AD[3] VCC HSS_TXFRAME0 VSS Ball W1 W2 W3 W4 W5 W6 Signal PCI_AD[1] VCCP HSS_RXFRAME0 VSS HSS_TXCLK1 HSS_RXFRAME1 Ball Y1 Y2 Y3 Y4 Y5 Y6 Signal HSS_TXCLK0 HSS_RXCLK0 HSS_TXFRAME1 VCC VCCP ETH_TXEN0
U21 U22 U23 U24 U25 U26
Note:
VCC GPIO[14] EX_RDY_N[1] EX_RDY_N[2] GPIO[15] EX_DATA[15]
V21 V22 V23 V24 V25 V26
GPIO[6] GPIO[9] VCC GPIO[13] VCCP EX_RDY_N[3]
W21 W22 W23 W24 W25 W26
GPIO[1] VCCP GPIO[8] VSS GPIO[11] GPIO[12]
Y21 Y22 Y23 Y24 Y25 Y26
RXDATA1 GPIO[0] VCC GPIO[5] VCCP GPIO[10]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 6 of 7)
Ball AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 Signal HSS_RXDATA0 VCCP VSS HSS_RXCLK1 ETH_TXDATA0[2] VCC ETH_RXDATA0[1] VSS N/C VCC Ball AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AA17 AA18 AA20 AA21 AA22 AA23 AA24 AA25 AA26
Note:
Signal HSS_TXDATA1 HSS_RXDATA1 ETH_TXDATA0[3] ETH_TXDATA0[1] VSS ETH_RXCLK0 VCCP N/C N/C VCCP VCCP VSS UTP_OP_DATA[7] VCCP UTP_OP_SOC VSS UTP_IP_DATA[6] VCCP UTP_IP_CLK UTP_IP_ADDR[1] VCCP CTS0_N CTS1_N VCCP GPIO[4]
Ball AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC16 AC18 AC19 AC20 AC22 AC23 AC24 AC25 AC26
Signal VSS ETH_TXDATA0[0] VCCP VCC ETH_RXDATA0[0] VSS VCC N/C VCC VCC VCCOSCP VCC RESET_IN_N VCC UTP_OP_FCI VCC UTP_IP_DATA[2] UTP_IP_SOC VCC JTG_TRST_N VCC RXDATA0 RTS1_N GPIO[2]
Ball AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD14 AD16 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26
Signal ETH_TXCLK0 ETH_RXDV0 VSS ETH_CRS0 ETH_MDC N/C N/C N/C VSS VSSOSCP VCCP PLL_LOCK UTP_OP_DATA[4] UTP_OP_DATA[2] VSS UTP_OP_ADDR[3] UTP_IP_DATA[7] VCCP UTP_IP_DATA[1] UTP_IP_ADDR[4] VSS JTG_TDO VSS TXDATA0 RTS0_N
AD13 PWRON_RESET_N
AC15 UTP_OP_DATA[1] AD15 AC17 UTP_OP_ADDR[1] AD17
VCC UTP_IP_FCI VSS VCC TXDATA1 VSS GPIO[3] VSS GPIO[7]
AB17 AB18 AB20 AB22 AB23 AB24 AB25 AB26
AA19 UTP_IP_ADDR[0] AB19
AB21 SCANTESTMODE_N AC21
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Table 23.
Ball Map Assignment for the Intel(R) IXP421 Network Processor (Sheet 7 of 7)
Ball AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE15 AE16 AE17 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Note:
Signal ETH_RXDATA0[3] VCCP ETH_COL0 N/C VCCP N/C VSS N/C VCCP VCCPLL1 VSS VCCPLL2 VCCP VSS UTP_OP_FCO VCCP VSS UTP_IP_DATA[4] VCCP UTP_IP_FCO VCCP JTG_TDI VCCP HIGHZ_N
Ball AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF15 AF16 AF17 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal ETH_RXDATA0[2] ETH_MDIO (Reserved) N/C N/C N/C N/C VSSOSC OSC_IN VSSOSCP OSC_OUT VCCOSC BYPASS_CLK UTP_OP_DATA[6] UTP_OP_DATA[3] UTP_OP_DATA[0] UTP_OP_CLK UTP_OP_ADDR[4] UTP_OP_ADDR[0] UTP_IP_DATA[5] UTP_IP_DATA[3] UTP_IP_DATA[0] UTP_IP_ADDR[3] UTP_IP_ADDR[2] JTG_TMS JTG_TCK
Ball
Signal
Ball
Signal
AE14 UTP_OP_DATA[5] AF14
AE18 UTP_OP_ADDR[2] AF18
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 1 of 7)
Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26
Note:
Signal PCI_AD[27] PCI_GNT_N[1] PCI_GNT_N[3] SDM_DATA[19] SDM_DATA[27] SDM_DATA[26] SDM_DATA[25] SDM_DATA[23] SDM_DATA[14] SDM_DATA[13] SDM_DATA[11] SDM_DATA[10] SDM_DATA[6] SDM_DATA[8] SDM_DQM[1] SDM_CS_N[0] SDM_CLKOUT SDM_RAS_N SDM_ADDR[12] SDM_ADDR[9] SDM_ADDR[8] SDM_ADDR[5] EX_RD_N EX_ADDR[1] EX_ADDR[3] EX_ADDR[5]
Ball B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26
Signal PCI_AD[28] VCCP PCI_GNT_N[2] VCCP SDM_DATA[28] VCCP SDM_DATA[21] VSS SDM_DATA[0] VCCP SDM_DATA[12] VSS SDM_DATA[9] VCCP SDM_DQM[2] VSS SDM_CKE VCCP SDM_ADDR[10] VSS SDM_ADDR[1] VCCP EX_IOWAIT_N VSS VCCP EX_ADDR[9]
Ball C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26
Signal PCI_AD[26] PCI_AD[30] VSS PCI_INTA_N VSS SDM_DATA[18] VSS VCCP SDM_DATA[24] VSS SDM_DATA[2] SDM_DATA[4] VSS SDM_DATA[7] SDM_DQM[3] VCCP SDM_CAS_N SDM_ADDR[11] VSS SDM_ADDR[6] SDM_ADDR[2] VSS EX_ADDR[0] EX_ADDR[4] EX_ADDR[7] EX_ADDR[13]
Ball D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26
Signal PCI_AD[25] VSS PCI_AD[31] VCC PCI_SERR_N VCC SDM_DATA[29] SDM_DATA[20] VCC SDM_DATA[15] SDM_DATA[1] VCC SDM_DATA[5] VCC SDM_WE_N SDM_CS_N[1] SDM_BA[1] VCC SDM_ADDR[0] VSS VCC EX_ALE VCC EX_ADDR[6] RCOMP EX_ADDR[17]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 2 of 7)
Ball E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E26
Note:
Signal PCI_AD[23] VCCP PCI_REQ_N[2] VSS PCI_GNT_N[0] SDM_DATA[16] VCCP SDM_DATA[30] VSS SDM_DATA[22] VCCP SDM_DATA[3] VSS SDM_DQM[0] VCCP SDM_BA[0] VSS SDM_ADDR[7] VCCP SDM_ADDR[3] USB_DNEG VCCP VSS EX_ADDR[10] EX_ADDR[15] EX_ADDR[19]
Ball F1 F2 F3 F4 F5 F6 F7 F8 F9 F10
Signal PCI_AD[20] PCI_IDSEL VCC PCI_REQ_N[0] VCCP VCC SDM_DATA[31] VSS SDM_DATA[17] VCC
Ball G1 G2 G3 G4 G5 G6
Signal PCI_AD[21] VCCP PCI_AD[24] VSS PCI_REQ_N[1] VSS
Ball H1 H2 H3 H4 H5 H6
Signal PCI_AD[16] PCI_AD[18] VCC PCI_CBE_N[3] VCC PCI_REQ_N[3]
F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
VCC SDM_ADDR[4] VSS USB_DPOS VCC EX_WR_N VCC EX_ADDR[14] VCCP EX_ADDR[21] G21 G22 G23 G24 G25 G26 EX_ADDR[2] VSS EX_ADDR[12] VSS EX_ADDR[20] EX_ADDR[22] H21 H22 H23 H24 H25 H26 VSS EX_ADDR[11] EX_ADDR[18] VCCP VSS EX_CS_N[1]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 3 of 7)
Ball J1 J2 J3 J4 J5 J6 Signal PCI_CLKIN VCCP VSS PCI_AD[22] VSS PCI_AD[29] Ball K1 K2 K3 K4 K5 K6 Signal PCI_CBE_N[2] VSS PCI_AD[17] VCCP PCI_AD[19] VCC Ball L1 L2 L3 L4 L5 Signal PCI_DEVSEL_N VCCP PCI_STOP_N VCC PCI_FRAME_N Ball M1 M2 M3 M4 M5 Signal PCI_CBE_N[1] PCI_PAR VSS PCI_IRDY_N VCCP
L11 L12 L13 L14 L15 L16
VSS VSS VSS VSS VSS VSS
M11 M12 M13 M14 M15 M16
VSS VSS VSS VSS VSS VSS
J21 J22 J23 J24 J25 J26
Note:
EX_ADDR[8] EX_ADDR[16] VCC EX_ADDR[23] EX_CS_N[2] EX_CS_N[4]
K21 K22 K23 K24 K25 K26
VCC VSS EX_CS_N[0] EX_CS_N[3] VCCP EX_CS_N[7] L22 L23 L24 L25 L26 VCCP VCC EX_CS_N[6] EX_DATA[0] EX_DATA[1] M22 M23 M24 M25 M26 EX_CS_N[5] EX_CLK EX_DATA[2] VSS EX_DATA[3]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 4 of 7)
Ball N1 N2 N3 N4 N5 Signal PCI_AD[11] VCCP VCC PCI_PERR_N PCI_AD[15] Ball P1 P2 P3 P4 P5 Signal PCI_CBE_N[0] PCI_AD[14] PCI_AD[13] VSS PCI_AD[12] Ball R1 R2 R3 R4 R5 Signal PCI_AD[10] VSS PCI_AD[9] VCC PCI_AD[4] Ball T1 T2 T3 T4 T5 Signal PCI_AD[6] PCI_TRDY_N VSS PCI_AD[2] VCCP
N11 N12 N13 N14 N15 N16
VSS VSS VSS VSS VSS VSS
P11 P12 P13 P14 P15 P16
VSS VSS VSS VSS VSS VSS
R11 R12 R13 R14 R15 R16
VSS VSS VSS VSS VSS VSS
T11 T12 T13 T14 T15 T16
VSS VSS VSS VSS VSS VSS
N22 N23 N24 N25 N26
Note:
VCC VSS VCC EX_DATA[4] EX_DATA[5]
P22 P23 P24 P25 P26
EX_DATA[6] EX_DATA[7] EX_DATA[8] VCCP EX_DATA[9]
R22 R23 R24 R25 R26
VCCP VCC EX_DATA[12] EX_DATA[11] EX_DATA[10]
T22 T23 T24 T25 T26
EX_RDY_N[0] VSS EX_DATA[14] VSS EX_DATA[13]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 5 of 7)
Ball U1 U2 U3 U4 U5 U6 Signal PCI_AD[8] VCCP PCI_AD[0] PCI_AD[7] N/C VCC Ball V1 V2 V3 V4 V5 V6 Signal PCI_AD[5] VSS PCI_AD[3] VCC N/C VSS Ball W1 W2 W3 W4 W5 W6 Signal PCI_AD[1] VCCP N/C VSS N/C N/C Ball Y1 Y2 Y3 Y4 Y5 Y6 Signal N/C N/C N/C VCC VCCP ETH_TXEN0
U21 U22 U23 U24 U25 U26
Note:
VCC GPIO[14] EX_RDY_N[1] EX_RDY_N[2] GPIO[15] EX_DATA[15]
V21 V22 V23 V24 V25 V26
GPIO[6] GPIO[9] VCC GPIO[13] VCCP EX_RDY_N[3]
W21 W22 W23 W24 W25 W26
GPIO[1] VCCP GPIO[8] VSS GPIO[11] GPIO[12]
Y21 Y22 Y23 Y24 Y25 Y26
RXDATA1 GPIO[0] VCC GPIO[5] VCCP GPIO[10]
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 6 of 7)
Ball AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 Signal N/C VCCP VSS N/C ETH_TXDATA0[2] VCC ETH_RXDATA0[1] VSS ETH_TXDATA1[1] VCC Ball AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25 AA26
Note:
Signal N/C N/C ETH_TXDATA0[3] ETH_TXDATA0[1] VSS ETH_RXCLK0 VCCP ETH_TXDATA1[2] ETH_RXDATA1[1] VCCP VCCP VSS N/C VCCP N/C VSS N/C VCCP N/C N/C VCCP CTS0_N CTS1_N VCCP GPIO[4]
Ball AC1 AC2 AC3 AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC22 AC23 AC24 AC25 AC26
Signal VSS ETH_TXDATA0[0] VCCP VCC ETH_RXDATA0[0] VSS VCC ETH_RXDATA1[2] VCC VCC VCCOSCP VCC RESET_IN_N VCC N/C N/C N/C VCC N/C N/C VCC JTG_TRST_N VCC RXDATA0 RTS1_N GPIO[2]
Ball AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26
Signal ETH_TXCLK0 ETH_RXDV0 VSS ETH_CRS0 ETH_MDC ETH_TXDATA1[0] ETH_RXDATA1[3] ETH_RXCLK1 VSS VSSOSCP VCCP PLL_LOCK N/C N/C VSS N/C N/C VCCP N/C N/C VSS JTG_TDO VSS TXDATA0 RTS0_N
AD13 PWRON_RESET_N
VCC N/C N/C VSS VCC TXDATA1 VSS GPIO[3] VSS GPIO[7]
AB17 AB18 AB19 AB20 AB22 AB23 AB24 AB25 AB26
AB21 SCANTESTMODE_N AC21
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 24.
Ball Map Assignment for the Intel(R) IXP420 Network Processor and Intel(R) IXC1100 Control Plane Processor (Sheet 7 of 7)
Ball AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26
Note:
Signal ETH_RXDATA0[3] VCCP ETH_COL0 ETH_TXEN1 VCCP ETH_RXDV1 VSS ETH_COL1 VCCP VCCPLL1 VSS VCCPLL2 VCCP N/C VSS N/C VCCP N/C VSS N/C VCCP N/C VCCP JTG_TDI VCCP HIGHZ_N
Ball AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Signal ETH_RXDATA0[2] ETH_MDIO (Reserved) ETH_TXDATA1[3] ETH_TXCLK1 ETH_RXDATA1[0] ETH_CRS1 VSSOSC OSC_IN VSSOSCP OSC_OUT VCCOSC BYPASS_CLK N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C N/C JTG_TMS JTG_TCK
Ball
Signal
Ball
Signal
Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, "Functional Signal Descriptions" on page 33.
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4.3
Package Thermal Specifications
The thermal characterization parameter "JT" is proportional to the temperature difference between the top, center of the package and the junction temperature. This can be a useful value for verifying device temperatures in an actual environment. By measuring the package of the device, the junction temperature can be estimated, if the thermal characterization parameter has been measured under similar conditions. The use of JT should not be confused with jc, which is the thermal resistance from the device junction to the external surface of the package or case nearest the die attachment -- as the case is held at a constant temperature. Case temperature = Junction Temperature - (JT * Power Dissipation) TJC = TJ - (JT * Power Dissipation) The case temperature can then be monitored to make sure that the maximum junction temperature is not violated. Examples are given in the following sections.
Note:
For more information on JT, refer to the EIA/JEDEC Standard 51-2, Section 4.
4.3.1
Commercial Temperature
"Commercial" temperature range is defined in terms of the ambient temperature range, which is specified as 0 C to 70 C. The maximum power (P) is 2.4 W and the maximum junction temperature (Tj) is 115 C.
JT for commercial temperature is 0.89 C/W.
Using the preceding junction-temperature formula, the commercial temperature for a 266 MHz device -- assuming a maximum power of 2 W -- would be: TJC = 115 C - (0.89 * 2.0) TJC = 113.22 C
4.3.2
Extended Temperature
"Extended" temperature range is defined in terms of the ambient temperature range, which is specified as -40 C to 85 C. The maximum power (P) is 2.4 W and the maximum junction temperature (Tj) is 115 C.
JT for extended temperature is 0.32 C/W.
Using the preceding junction-temperature formula, the extended temperature for a 533 MHz device -- assuming a maximum power of 2.4 W -- would be: TJC = 115 C - (0.32 * 2.4) TJC = 114.23 C
Datasheet Document Number: 252479, Revision: 005
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5.0
5.1
Electrical Specifications
Absolute Maximum Ratings
Parameter Ambient Air Temperature (Extended) Ambient Air Temperature (Commercial) Supply Voltage Core Supply Voltage I/O Supply Voltage Oscillator (VCCOSC) Supply Voltage Oscillator (VCCOSCP) Supply Voltage PLL (VCCPLL1) Supply Voltage PLL (VCCPLL2) Voltage On Any I/O Ball Storage Temperature Maximum Rating -40 C to 85 C 0 C to 70 C -0.3 V to 2.1V -0.3 V to 3.6V -0.3 V to 2.1V -0.3 V to 3.6V -0.3 V to 2.1V -0.3 V to 2.1V -0.3 V to 3.6V -55o C to 125o C
Warning:
Stressing the device beyond the "absolute maximum ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability.
5.2
VCCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements
To reduce voltage-supply noise on the analog sections of the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (VCCPLL1, VCCPLL2) and oscillator circuit (VCCOSCP, VCCOSC) require isolated voltage supplies. The filter circuits for each supply are shown in the following sections.
5.2.1
VCCPLL1 Requirement
A parallel combination of a 10-nF capacitor -- for bypass -- and a 200-nF capacitor -- for a firstorder filter with a cut-off frequency below 30 MHz -- must be connected to the VCCPLL1 pin of the Intel(R) IXP42X product line and IXC1100 control plane processors. The ground of both capacitors should be connected to the nearest VSS supply pin. Both capacitors should be located less than 0.5 inch away from the VCCPLL1 pin and the associated VSS pin. In order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 9.
VCCPLL1 Power Filtering Diagram
1.3 V VCCPLL1 10 nF 100 nF 100 nF VSS VSS
B1680-03 Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
5.2.2
VCCPLL2 Requirement
A parallel combination of a 10-nF capacitor -- for bypass -- and a 200-nF capacitor -- for a firstorder filter with a cut-off frequency below 30 MHz -- must be connected to the VCCPLL2 pin of the IXP42X product line and IXC1100 control plane processors. The ground of both capacitors should be connected to the nearest VSS supply pin. Both capacitors should be located less than 0.5 inch away from the VCCPLL2 pin and the associated VSS pin. In order to achieve the 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other.
Figure 10.
VCCPLL2 Power Filtering Diagram
1.3 V VCCPLL2 10 nF 100 nF 100 nF VSS VSS
B1681-03 Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
5.2.3
VCCOSCP Requirement
A single 170-nF capacitor must be connected between the VCCP_OSC pin and VSSP_OSC pin of the IXP42X product line and IXC1100 control plane processors. This capacitor value provides both bypass and filtering.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
When 170 nF is an inconvenient size, capacitor values between 150 nF to 200 nF could be used with little adverse effects, assuming that the effective series resistance of the 200-nF capacitor is under 50 m. In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other. VSSP_OSC consists of two pins, AD10 and AF10. Ensure that both pins are connected as shown in Figure 11. Figure 11. VCCOSCP Power Filtering Diagram
3.3 V VCCOSCP 170 nF VSSOSCP VSS VSSOSCP
Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
B1675-04
5.2.4
VCCOSC Requirement
A parallel combination of a 10-nF capacitor -- for bypass -- and a 200-nF capacitor -- for a firstorder filter with a cut-off frequency below 33 MHz -- must be connected to both of the VCCOSC pins of the IXP42X product line and IXC1100 control plane processors. The grounds of both capacitors should be connected to the VSSOSC supply pin. Both capacitors should be located less than 0.5 inch away from the VCCOSC pin and the associated VSSOSC pin. In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF capacitors may be used as long as the capacitors are placed directly beside each other.
Figure 12.
VCCOSC Power Filtering Diagram
1.3 V
Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
10 nF
100 nF
100 nF
VSS
B1676-03
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.3
RCOMP Pin Requirements
Figure 13 shows the requirements for the RCOMP pin.
Figure 13.
RCOMP Pin External Resistor Requirements
RCOMP Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
34 , + 1%
VSS VSS
B1672-02
5.4
5.4.1
Table 25.
DC Specifications
Operating Conditions
Operating Conditions
Symbol VCCP VCC VCCOSC VCCOSCP VCCPLL1 VCCPLL2 Parameter Voltage supplied to the I/O. Voltage supplied to the internal logic. Voltage supplied to the internal oscillator logic. Voltage supplied to the oscillator I/O. Voltage supplied to the analog phase-lock loop. Voltage supplied to the analog phase-lock loop. Min. 3.135 1.235 1.235 3.135 1.235 1.235 Typ. 3.3 1.3 1.3 3.3 1.3 1.3 Max. 3.465 1.365 1.365 3.465 1.365 1.365 Units V V V V V V Notes
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.4.2
Table 26.
PCI DC Parameters
PCI DC Parameters
Symbol VIH VIL VOH VOL IIL CIN COUT CIDSEL LPIN Notes: 1. 2. 3. 4. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance I/O or output pin capacitance IDSEL-pin capacitance Pin inductance IOUT = -500 A IOUT = 1500 A 0 < VIN < VCCP -10 5 5 5 20 0.9 VCCP 0.1 VCCP 10 Conditions Min. 0.5 VCCP 0.3 VCCP Typ. Max. Units V V V V A pF pF pF nH Notes 4 3 3 3 1, 3 2, 3 2, 3 2, 3 2, 3
Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs. These values are typical values seen by the manufacturing process and are not tested. For additional information, see the PCI Local Bus Specification, Rev. 2.2. Please refer to the product specification update.
5.4.3
Table 27.
USB DC Parameters
USB v1.1 DC Parameters
Symbol VIH VIL VOH VOL IIL CIN Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance IOUT = -6.1 * VOHmA IOUT = 6.1 * VOHmA 0 < VIN < VCCP -10 5 2.8 0.3 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF 2 Notes 1
Notes: 1. Please refer to the product specification update. 2. These values are typical values seen by the manufacturing process and are not tested
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5.4.4
Table 28.
UTOPIA-2 DC Parameters
UTOPIA-2 DC Parameters
Symbol VIH VIL VOH VOL IOH IOL IIL CIN COUT Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Output current at high voltage Output current at low voltage Input-leakage current Input-pin capacitance I/O or output pin capacitance IOUT = -8 mA IOUT = 8 mA VOH > 2.4 V VOL < 0.5 V 0 < VIN < VCCP -8 8 -10 5 5 10 2.4 0.5 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V mA mA A pF pF 1 2 2 Notes
Notes: 1. Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs. 2. These values are typical values seen by the manufacturing process and are not tested.
5.4.5
Table 29.
MII DC Parameters
MII DC Parameters
Symbol VIH VIL VOH VOL IOH IOL IIL CIN Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Output current at high voltage Output current at low voltage Input-leakage current Input-pin capacitance IOUT = -4 mA IOUT = 4mA VOH > 2.4 V VOL < 0.4 V 0 < VIN < VCCP -8 8 -10 5 10 2.4 0.4 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V mA mA A pF 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.4.6
Table 30.
MDIO DC Parameters
MDIO DC Parameters
Symbol VIH VIL VOH VOL IIL CIN CINMDIO Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance Input-pin capacitance IOUT = -4 mA IOUT = 4 mA 0 < VIN < VCCP -10 5 5 2.4 0.4 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF pF 1 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
5.4.7
Table 31.
SDRAM Bus DC Parameters
SDRAM Bus DC Parameters
Symbol VIH VIL VOH
VOL
Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Output-leakage current Input-pin capacitance I/O-pin capacitance
Conditions
Min. 2.0
Typ.
Max.
Units V
Notes 1 2
0.8 IOUT = -4 mA IOUT = 4 mA 0 < VIN < VCCP 0 < VIN < VCCP -5 -5 4 5 2.4 0.4 5 5
V V V A A pF pF
IIL IOL CINCLK CIO
3 3
Notes: 1. VIH overshoot: VIH (MAX) = VCCP + 2 V for a pulse width < 3 ns, and the pulse width cannot be greater than one third of the cycle rate. 2. VIL undershoot: VIL (MIN) = -2 V for a pulse width < 3 ns cannot be exceeded. 3. These values are typical values seen by the manufacturing process and are not tested.
5.4.8
Table 32.
Expansion Bus DC Parameters
Expansion Bus DC Parameters (Sheet 1 of 2)
Symbol VIH VIL VOH Parameter Input-high voltage Input-low voltage Output-high voltage IOUT = -4 mA 2.4 Conditions Min. 2.0 0.8 Typ. Max. Units V V V 1 Notes
Notes: 1. Test conditions were a 70 pF load to ground. 2. These values are typical values seen by the manufacturing process and are not tested.
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Table 32.
Expansion Bus DC Parameters (Sheet 2 of 2)
Symbol VOL IIL CIN Parameter Output-low voltage Input-leakage current Input-pin capacitance Conditions IOUT = 4mA 0 < VIN < VCCP -10 5 Min. Typ. Max. 0.4 10 Units V A pF 2 Notes 1
Notes: 1. Test conditions were a 70 pF load to ground. 2. These values are typical values seen by the manufacturing process and are not tested.
5.4.9
Table 33.
High-Speed, Serial Interface 0 DC Parameters
High-Speed, Serial Interface 0 DC Parameters
Symbol VIH VIL VOH VOL IIL CIN Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance IOUT = -8 mA IOUT = 8 mA 0 < VIN < VCCP -10 5 2.4 0.4 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
5.4.10
Table 34.
High-Speed, Serial Interface 1 DC Parameters
High-Speed, Serial Interface 1 DC Parameters
Symbol VIH VIL VOH VOL IIL CIN Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance IOUT = -8 mA IOUT = 8 mA 0 < VIN < VCCP -10 5 2.4 0.4 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.4.11
Table 35.
High-Speed and Console UART DC Parameters
UART DC Parameters
Symbol VIH VIL VOH VOL IIL CIN Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance IOUT = -4 mA IOUT = 4 mA 0 < VIN < VCCP -10 5 2.4 0.4 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
5.4.12
Table 36.
GPIO DC Parameters
GPIO DC Parameters
Symbol VIH VIL VOH VOL VOH VOL IIL CIN Parameter Input-high voltage Input-low voltage Output-high voltage for GPIO 0 to GPIO 13 Output-low voltage for GPIO 0 to GPIO 13 Output-high voltage for GPIO 14 and GPIO 15 Output-low voltage for GPIO 14 and GPIO 15 Input-leakage current Input-pin capacitance IOUT = -16 mA IOUT = 16 mA IOUT = -4 mA IOUT = 4 mA 0 < VIN < VCCP -10 5 2.4 0.4 10 2.4 0.4 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V V V A pF Notes
5.4.13
Table 37.
JTAG DC Parameters
JTAG DC Parameters
Symbol VIH VIL VOH VOL IIL CIN Note: 1. Parameter Input-high voltage Input-low voltage Output-high voltage Output-low voltage Input-leakage current Input-pin capacitance IOUT = -4 mA IOUT = 4 mA 0 < VIN < VCCP -10 5 2.4 0.4 10 Conditions Min. 2.0 0.8 Typ. Max. Units V V V V A pF 1 Notes
These values are typical values seen by the manufacturing process and are not tested.
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5.4.14
Table 38.
Reset DC Parameters
PWRON_RESET_N DC Parameters
Symbol Parameter Conditions Min. Typ. Max. Units Notes The input voltage must not exceed 1.3V or long-term reliability may be adversely affected.
VIH
Input-high voltage
1.0
1.3
V
VIL IIL CIN
Input-low voltage Input leakage current Input Capacitance 0 < VIN < 1.3V -500
0.3 10 1
V A pF Simulated results.
5.5
5.5.1
5.5.1.1
AC Specifications
Clock Signal Timings
Processor Clock Timings
Crystal oscillators require that good system-level design practices be followed for reliable start-up and oscillation. Please refer to the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Product Line: Crystal Design Considerations Application Note (Document Number 305588), and contact Intel for the recommended Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor part number optimized for use with crystal oscillators.
Table 39.
Device Clock Timings (Oscillator Reference) (Sheet 1 of 2)
Symbol VIH VIL TFREQUENCY
FREQUENCY
Parameter Input-high voltage Input-low voltage Clock frequency for IXP42X product line and IXC1100 control plane processors crystal or oscillator. Clock tolerance over -40 C to 85 C. Pin capacitance of IXP42X product line and IXC1100 control plane processors' inputs. CSHUNT is a crystal parameter sometimes referred to as the holder capacitance.
Min. 2.0
Nom.
Max.
Units V
Notes
0.8 33.33 -50 5 2 3 4 50
V MHz ppm pF pF 1, 4
CIN CSHUNT
Notes: 1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. Use the component values recommended by the crystal manufacturer. 3. This parameter applies when driving the clock input with an oscillator. 4. Where the IXP42X product line or IXC1100 control plane processor is configured with an input reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation. To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to be within the specified range at an input clock frequency of 33.33 MHz.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 39.
Device Clock Timings (Oscillator Reference) (Sheet 2 of 2)
Symbol C1 C2 TDC Parameter Load capacitance Load capacitance Duty cycle 35 50 65 Min. Nom. Max. Units pF pF % Notes 2 2 3
Notes: 1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. Use the component values recommended by the crystal manufacturer. 3. This parameter applies when driving the clock input with an oscillator. 4. Where the IXP42X product line or IXC1100 control plane processor is configured with an input reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation. To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to be within the specified range at an input clock frequency of 33.33 MHz.
.
Table 40.
Device Clock Timings (Crystal Reference)
Symbol VIH VIL TFREQUENCY
FREQUENCY
Parameter Input-high voltage Input-low voltage Clock frequency for IXP42X product line and IXC1100 control plane processors crystal or oscillator. Clock tolerance over -40 C to 85 C. Equivalent Series Resistance Pin capacitance of IXP42X product line and IXC1100 control plane processors' inputs. CSHUNT is a crystal parameter sometimes referred to as the holder capacitance. Load capacitance Load capacitance Duty cycle
Min. 1.9
Nom.
Max.
Units V
Notes
1.6 33.33 -50 50 60 5
V MHz ppm pF 1, 4
ESR CIN
CSHUNT C1 C2 TDC
2
3
4
pF pF pF 2 2 3
35
50
65
%
Notes: IMPORTANT NOTE: Please refer to the product specification update regarding new crystal specifications. 1. This value could be an oscillator input or a series resonant frequency from a crystal. If used as an oscillator input, tie to the crystal input pin and leave the crystal output pin disconnected. 2. Use the component values recommended by the crystal manufacturer. 3. This parameter applies when driving the clock input with an oscillator. 4. Where the IXP42X product line or IXC1100 control plane processor is configured with an input reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation. To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to be within the specified range at an input clock frequency of 33.33 MHz.
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Figure 14.
Typical Connection to a Crystal
Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
OSC_IN C1 XTAL
OSC_OUT C2
B1677-03
Figure 15.
Typical Connection to an Oscillator
Intel(R) IXP42X Product Line / Intel(R) IXC1100 Control Plane Processor
OSC_IN
Oscillator
OSC_OUT
B1678-03
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.1.2
Table 41.
PCI Clock Timings
PCI Clock Timings
33 MHz Symbol TPERIODPCICLK TCLKHIGH TCLKLOW TRISE/FALL Parameter Min. Clock period for PCI Clock PCI Clock high time PCI Clock low time Rise and fall time requirements for PCI Clock 30 11 11 2 Max. Min. 15 6 6 2 Max. ns ns ns ns 66 MHz Units Notes
5.5.1.3
Table 42.
MII Clock Timings
MII Clock Timings
Symbol Tperiod100Mbit Tperiod10Mbit Tduty Trise/fall Parameter Clock period for Tx and Rx Ethernet clocks Clock period for Tx and Rx Ethernet clocks Duty cycle for Tx and Rx Ethernet clocks Rise and fall time requirements for Tx and Rx Ethernet clocks 35 Min. Nom. 25 2.5 50 Max. 25 2.5 65 2 Units MHz MHz % ns Notes
5.5.1.4
Table 43.
UTOPIA-2 Clock Timings
UTOPIA-2 Clock Timings
Symbol Tperiod Tduty Trise/fall Note: 1. Parameter Clock period for Tx and Rx UTOPIA-2 clocks Duty cycle for Tx and Rx UTOPIA-2 clocks Rise and fall time requirements for Tx and Rx UTOPIA-2 clocks 40 50 Min. Nom. Max. 33 60 2 Units MHz % ns Notes 1 1 1
The UTOPIA interface can operate at a minimum frequency greater than 0 Hz.
5.5.1.5
Table 44.
Expansion Bus Clock Timings
Expansion Bus Clock Timings
Symbol Tperiod Tduty Trise/fall Parameter Clock period for expansion-bus clock Duty cycle for expansion-bus clock Rise and fall time requirements for expansion-bus clock 40 50 Min. Nom. Max. 66 60 2 Units MHz % ns Notes
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5.5.2
Bus Signal Timings
The AC timing waveforms are shown in the following sections.
5.5.2.1
Figure 16.
PCI
PCI Output Timing
Vhi
CLK
Vlow Tclk2out(b)
Output Delay
A9572-01
Note:
VHI = 0.6 VCC and VLOW = 0.2 VCC
Figure 17.
PCI Input Timing
CLK
Tsetup(b)
Thold
Input
Inputs Valid
A9573-01
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 45.
PCI Bus Signal Timings
33 MHz Symbol Parameter Min. Clock to output for all bused signals. This is the PCI_AD[31:0], PCI_CBE_N [3:0], PCI_PAR, PCI_FRAME_N, PCI_IRDY_N, PCI_TRDY_N, PCI_STOP_N, PCI_DEVSEL_N, PCI_PERR_N, PCI_SERR_N Clock to output for all point-to-point signals. This is the PCI_GNT_N and PCI_REQ_N(0) only. Input setup time for all bused signals. This is the PCI_AD[31:0], PCI_CBE_N [3:0], PCI_PAR, PCI_FRAME_N, PCI_IRDY_N, PCI_TRDY_N, PCI_STOP_N, PCI_DEVSEL_N, PCI_PERR_N, PCI_SERR_N Input setup time for all point-topoint signals. This is the PCI_REQ_N and PCI_GNT_N(0) only. Input hold time from clock. Reset active-to-output float delay Max. Min. Max. 66 MHz Units Notes
Tclk2outb
2
11
1
6
ns
1, 2, 5, 7, 8
Tclk2out
2
12
1
6
ns
1, 2, 5, 7, 8
Tsetupb
7
3
ns
4, 6, 7, 8
Tsetup Thold Trst-off
10, 12
5
ns
4, 7, 8
0 40
0 40
ns ns
4, 7, 8 5, 6, 7, 8
Notes: 1. See the timing measurement conditions. 2. Parts compliant to the 3.3 V signaling environment. 3. REQ# and GNT# are point-to-point signals and have different output valid delay and input setup times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has a setup of 12 ns for 33 MHz and 5 ns for 66 MHz. 4. RST# is asserted and de-asserted asynchronously with respect to CLK. 5. All PCI outputs must be asynchronously driven to a tri-state value when RST# is active. 6. Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time. 7. Timing was tested with a 70-pF capacitor to ground. 8. For additional information, see the PCI Local Bus Specification, Rev. 2.2.
5.5.2.2
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and IXC1100 control plane processors' USB 1.1 interface is a device or function controller only. The IXP42X product line and IXC1100 control plane processors' USB v 1.1 interface cannot be line-powered.
March 2005 96
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5.5.2.3
Figure 18.
UTOPIA-2
UTOPIA-2 Input Timings
Clock
Signals
Tsetup Thold
A9578-01
Table 46.
UTOPIA-2 Input Timings Values
Symbol Parameter Input setup prior to rising edge of clock. Inputs included in this timing are UTP_IP_DATA[7:0], UTP_IP_SOC, AND UTP_IP_FCI, and UTP_OP_FCI. Input hold time after the rising edge of the clock. Inputs included in this timing are UTP_IP_DATA[7:0], UTP_IP_SOC, and UTP_IP_FCI, and UTP_OP_FCI. Min. Max. Units Notes
Tsetup
8
ns
Thold
1
ns
Figure 19.
UTOPIA-2 Output Timings
Clock
Signals
Tclk2out Tholdout
A9579-01
Table 47.
UTOPIA-2 Output Timings Values
Symbol Parameter Rising edge of clock to signal output. Outputs included in this timing are UTP_IP_DATA[3:0], UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. Signal output hold time after the rising edge of the clock. Outputs included in this timing are UTP_IP_DATA[3:0], UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO, UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0]. Min. Max. Units Notes
Tclk2out
17
ns
1
Tholdout
1
ns
1
Note: 1.
Timing was tested with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 97
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.4
Figure 20.
MII
MII Output Timings
T1 T2
eth_tx_clk eth_tx_data[7:0] eth_tx_en eth_crs
A9580-01
Table 48.
MII Output Timings Values
Symbol T1 T2 Note: 1. Parameter Clock to output delay for ETH_TXDATA and ETH_TXEN. ETH_TXDATA and ETH_TXEN hold time after ETH_TXCLK. Min. 0 2 Max. 17 Units ns ns Notes 1
These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.
Figure 21.
MII Input Timings
T3 T4
eth_rx_clk eth_rx_data[7:0] eth_rx_dv eth_crs
A9581-01
Table 49.
MII Input Timings Values
Symbol T3 T4 Parameter ETH_RXDATA and ETH_RXDV setup time prior to rising edge of ETH_RXCLK ETH_RXDATA and ETH_RXDV hold time after the rising edge of ETH_RXCLK Min. 5.5 0 Max. Units ns ns Notes 1, 2 1, 2, 3
Notes: 1. These values satisfy the MII specification requirement of 10-ns setup and hold time. 2. Timing tests were performed with a 70-pF capacitor to ground. 3. This parameter has been simulated but has not been fully tested.
March 2005 98
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.5
Figure 22.
MDIO
MDIO Output Timings
ETH_MDC
T1 T2
ETH_MDIO
A9582-02
Note:
NPE is sourcing MDIO.
Figure 23.
MDIO Input Timings
T5
ETH_MDC
T3 T4
ETH_MDIO
A9583-02
Note:
PHY is sourcing MDIO.
Table 50.
MDIO Timings Values
Symbol T1 T2 T3 T4 T5 Note: 1. Parameter ETH_MDIO, clock to output timing with respect to rising edge of ETH_MDC clock ETH_MDIO output hold timing after the rising edge of ETH_MDC clock ETH_MDIO input setup prior to rising edge of ETH_MDC clock ETH_MDIO hold time after the rising edge of ETH_MDC clock ETH_MDC clock period 10 2 0 125 500 Min. Max. ETH_MDC/2 + 10 ns Units ns ns ns ns ns 1 Notes
This parameter is guaranteed by design but has not been 100% tested.
Datasheet Document Number: 252479, Revision: 005
March 2005 99
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.6
Figure 24.
SDRAM Bus
SDRAM Input Timings
Clock Signals
Tsetup Thold
B4891-01
Table 51.
SDRAM Input Timings Values
Symbol Tsetup Parameter Input setup prior to rising edge of clock. Inputs included in this timing are SDM_DQ[31:0] (during a read operation). Input hold time after the rising edge of the clock. Inputs included in this timing are SDM_DQ[31:0] (during a read operation). Min. 1.4 Max. Units ns Notes
Thold
1.5
ns
Figure 25.
SDRAM Output Timings
Clock
Signals
Tclk2out
Data Valid
Tholdout
A9584-01
Table 52.
SDRAM Output Timings Values
Symbol Parameter Rising edge of clock-to-signal output. Outputs included in this timing are SDM_ADDR[12:0], SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE, SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N, SDM_RAS_N, SDM_DQ[31:0] (during a write operation). Signal output hold time after the rising edge of the clock. Outputs included in this timing are SDM_DQ[31:0] (during a write operation). Timing test were performed with a 70-pF load to ground. 1.5 Min. Max. Units Notes
Tclk2out
5.5
ns
1
Tholdout Note: 1.
ns
1
March 2005 100
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.7
Figure 26.
Expansion Bus
Signal Timing With Respect to Clock Rising Edge
T1
1-4 Cycles
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
T OV
EX_CS_N[0]
EX_ADDR[23:0] EX_IOWAIT_N
Valid Address T OV
EX_RD_N
T setup
EX_DATA[15:0]
T hold
Data In
EX_WR_N
T OV Data Out
B4870-002
EX_DATA[15:0]
Table 53.
Signal Timing With Respect to Clock Rising Edge
Symbol Tov Tsetup Thold Note: 1. Description Control signal and data output valid after clock rising edge Input Setup time with respect to clock rising edge. Input Hold time with respect to clock rising edge. The Setup and Hold Timing Values are for all modes. 3 2 Min. Max. 15 Units ns ns ns 1 1 Notes
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 27.
Intel(R) Multiplexed Read Mode
Intel(R) Multiplexed Read Mode T1
2-5 Cycles ALE Extended EX_CLK
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
Valid Address
EX_ALE
EX_IOWAIT_N
Trdsetup
EX_RD_N
Trdhold
EX_DATA[15:0]
Valid Address
Valid Data
B3747-001
March 2005 102
Datasheet Document Number: 252479, Revision: 005
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 28.
Intel(R) Multiplexed Write Mode
Intel(R) Multiplexed Write Mode T1
2-5 Cycles ALE Extended EX_CLK
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
Valid Address
EX_ALE
EX_IOWAIT_N
Tdhold2afterwr Twrpulse Tdval2valwrt
EX_WR_N
Tale2addrhold Valid Address
EX_DATA[15:0]
Valid Data
B3748-001
Datasheet Document Number: 252479, Revision: 005
March 2005 103
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 54.
Intel(R) Multiplexed Mode Values
Symbol Parameter Min. Max. Units Notes
Talepulse Tale2addrhold Tdval2valwrt Twrpulse Tdholdafterwr Tale2valcs Trdsetup Trdhold Trecov
Pulse width of EX_ALE (ADDR is valid at the rising edge of EX_ALE) Valid address hold time after from falling edge of EX_ALE Write data valid prior to EX_WR_N falling edge Pulse width of the EX_WR_N Valid data after the rising edge of EX_WR_N Valid chip select after the falling edge of EX_ALE Data valid required before the rising edge of EX_RD_N Data hold required after the rising edge of EX_RD_N Time needed between successive accesses on expansion interface.
1 1 1 1 1 1 15 0 1
41 1 4 16 4 4
Cycles Cycles Cycles Cycles Cycles Cycles ns ns
1, 7 1, 2, 7 3, 7 4, 7 5, 7 7
16
Cycles
6
Notes: 1. The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing parameter. The parameter Tale2addrhold is fixed at 1 cycle. 2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device. 3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or write) to an external device. Data will be available during this time as well. 5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the expansion interface. 7. One cycle is the period of the Expansion Bus clock. 8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. Timing tests were performed with a 70-pF capacitor to ground.
March 2005 104
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 29.
Intel(R) Simplex Read Mode
Intel(R) Simplex Read Mode
T1
1-4 Cycles
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
EX_ADDR[23:0]
Valid Address
EX_IOWAIT_N
Trdsetup
EX_RD_N
Trdhold Valid Data
EX_DATA[15:0]
B3749-002
Figure 30.
Intel(R) Simplex Write Mode
Intel(R) Simplex Write Mode
T1
1-4 Cycles
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
EX_ADDR[23:0]
Valid Address
EX_IOWAIT_N
Tdhold2afterwr Twrpulse Taddr2valcs Tdval2valwrt
EX_WR_N
EX_DATA[15:0]
Valid Data
B3750-002
Datasheet Document Number: 252479, Revision: 005
March 2005 105
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 55.
Intel Simplex Mode Values
Symbol Parameter Min. Max. Units Notes
Taddr2valcs Tdval2valwrt Twrpulse Tdholdafterwr Trdsetup Trdhold Trecov
Valid address to valid chip select Write data valid prior to EX_WR_N falling edge Pulse width of the EX_WR_N Valid data after the rising edge of EX_WR_N Data valid required before the rising edge of EX_RD_N Data hold required after the rising edge of EX_RD_N Time required between successive accesses on the expansion interface.
1 1 1 1 15 0 1
4 4 16 4
Cycles Cycles Cycles Cycles ns ns
1, 2, 7 3, 7 4, 7 5, 7
16
Cycles
6
Notes: 1. EX_ALE is not valid in simplex mode of operation. 2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device. 3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or write) to an external device. Data will be available during this time as well. 5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the expansion interface. 7. One cycle is the period of the Expansion Bus clock. 8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. Timing tests were performed with a 70-pF capacitor to ground.
March 2005 106
Datasheet Document Number: 252479, Revision: 005
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 31.
Motorola* Multiplexed Read Mode
Motorola* Multiplexed Read Mode
T1
2-5 Cycles ALE Extended
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs Valid Address
EX_ADDR[23:0]
EX_ALE EX_IOWAIT_N
EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0]
Trdsetup Trdhold Valid Address Valid Data
B3751-001
Datasheet Document Number: 252479, Revision: 005
March 2005 107
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 32.
Motorola* Multiplexed Write Mode
Motorola* Multiplexed Write Mode
T1
2-5 Cycles ALE Extended
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs Valid Address
EX_ADDR[23:0]
EX_ALE
EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0]
Tale2addrhold Valid Address
Tdval2valds
Tdspulse
Valid Data
B3752-001
March 2005 108
Datasheet Document Number: 252479, Revision: 005
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 56.
Motorola* Multiplexed Mode Values
Symbol Parameter Min. Max. Units Notes
Talepulse Tale2addrhold Tdval2valds Tdspulse Tdholdafterds Tale2valcs Trdsetup Trdhold Trecov
Pulse width of EX_ALE (ADDR is valid at the rising edge of EX_ALE) Valid address hold time after from falling edge of EX_ALE Write data valid prior to EXP_MOT_DS_N falling edge Pulse width of the EXP_MOT_DS_N Valid data after the rising edge of EXP_MOT_DS_N Valid chip select after the falling edge of EX_ALE Data valid required before the rising edge of EXP_MOT_DS_N Data hold required after the rising edge of EXP_MOT_DS_N Time needed between successive accesses on expansion interface.
1 1 1 1 1 1 15 0 1
4 1 4 16 4 4
Cycles Cycles Cycles Cycles Cycles Cycles ns ns
1, 7 1, 2, 7 3, 7 4, 7 5, 7 7
16
Cycles
6
Notes: 1. The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing parameter. The parameter Tale2addrhold is fixed at 1 cycle. 2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device. 3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or write) to an external device. Data will be available during this time as well. 5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the expansion interface. 7. One cycle is the period of the Expansion Bus clock. 8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 109
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 33.
Motorola* Simplex Read Mode
Motorola* Simplex Read Mode
T1
1-4 Cycles
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Tad2valcs
EX_ADDR[23:0]
Valid Address
EX_ALE
EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0]
Trdsetup Trdhold Valid Data
B3753-001
March 2005 110
Datasheet Document Number: 252479, Revision: 005
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 34.
Motorola* Simplex Write Mode
Motorola* Simplex Write Mode
T1
1-4 Cycles
T2
1-4 Cycles
T3
1-16 Cycles
T4
1-4 Cycles
T5
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Tad2valcs
EX_ADDR[23:0]
Valid Address
EX_ALE
EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0]
Tdhold2afterds
Tdspulse Tdval2valds
Valid Data
B3754-001
Datasheet Document Number: 252479, Revision: 005
March 2005 111
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 57.
Motorola* Simplex Mode Values
Symbol Parameter Min. Max. Units Notes
Tad2valcs Tdval2valds Tdspulse Tdholdafterds Trdsetup Trdhold Trecov
Valid address to valid chip select Write data valid prior to EXP_MOT_DS_N falling edge Pulse width of the EXP_MOT_DS_N Valid data after the rising edge of EXP_MOT_DS_N Data valid required before the rising edge of EXP_MOT_DS_N Data hold required after the rising edge of EXP_MOT_DS_N Time required between successive accesses on the expansion interface.
1 1 1 1 15 0 1
4 4 16 4
Cycles Cycles Cycles Cycles ns ns
1, 2, 7 3, 7 4, 7 5, 7
16
Cycles
6
Notes: 1. EX_ALE is not valid in simplex mode of operation. 2. Setting the address phase parameter (T1) will adjust the duration that the address appears to the external device. 3. Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a data strobe (read or write) to an external device. 4. Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read or write) to an external device. Data will be available during this time as well. 5. Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects, address, and data (during a write) will be held. 6. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the expansion interface. 7. One cycle is the period of the Expansion Bus clock. 8. Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in synchronous mode. 9. Timing tests were performed with a 70-pF capacitor to ground.
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Datasheet Document Number: 252479, Revision: 005
Figure 35.
Datasheet
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-8 Mode Read Accesses T2 T3 T4
T5
1-16 Cycles
EX_CLK
Trecov Taddsetup Valid Address
HPI-8 Mode Read Accesses
EX_CS_N[0] (hcs_n)
EX_ADDR[23:0] (hcntl)
EX_RD_N (hr_w_n)
EX_ADDR[0] (hbil)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
EX_RDY_N (hrdy)
Tdata_setup Valid Data
Tdata_hold
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
EX_DATA[15:0] (hdout)
B3742-001
March 2005 113
Figure 36.
March 2005 114
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-8 Mode Write Accesses T2 T3 T4
T5
1-16 Cycles
EX_CLK
Trecov Taddsetup Valid Address
HPI-8 Mode Write Accesses
EX_CS_N[0] (hcs_n)
EX_ADDR[23:0] (hcntl)
EX_RD_N (hr_w_n)
EX_ADDR[0] (hbil)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
EX_RDY_N (hrdy)
Tdata_setup Valid Data
Tdata_hold
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
EX_DATA[15:0] (hdin)
B3746-001
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 58.
HPI Timing Symbol Description
State Description Min. Max. Unit Notes
T1 T2 T3 T4 T5
Address Timing Setup/Chip Select Timing Strobe Timing Hold Timing Recovery Phase
3 3 2 3 2
4 4 16 4 17
Cycles Cycles Cycles Cycles Cycles
1, 5, 6 2, 6 3, 5, 6 6 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Table 59.
HPI-8 Mode Write Access Values
Symbol Parameter Min. Max. Units Notes
Tadd_setup Tcs2hds1val Thds1_pulse
Valid time that address is asserted on the line. The address is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe being active. Pulse width of the HDS1 data strobe
11 3 4
45 4 5
Cycles Cycles Cycles
1, 5, 6 5, 6 2, 4, 5
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 115
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 59.
HPI-8 Mode Write Access Values
Symbol Parameter Min. Max. Units Notes
Tdata_setup Tdata_hold Trecov
Data valid prior to the rising edge of the HDS1 data strobe. Data valid after the rising edge of the HDS1 data strobe. Time required between successive accesses on the expansion interface.
4 4 2
5 36 17
Cycles Cycles Cycles
3, 5, 6 3, 6 4, 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
March 2005 116
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 60.
HPI-16 Multiplexed Write Accesses Values
Symbol Parameter Min. Max. Units Notes
Tadd_setup Tcs2hds1val Thds1_pulse Tdata_setup Tdata_hold Trecov
Valid time that address is asserted on the line. The address is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe being active. Pulse width of the HDS1 data strobe. Data valid prior to the rising edge of the HDS1 data strobe. Data valid after the rising edge of the HDS1 data strobe. Time required between successive accesses on the expansion interface.
11 3 4 4 4 2
45 4 5 5 36 17
Cycles Cycles Cycles Cycles Cycles Cycles
1, 5, 6 5, 6 2, 4, 5 3, 5, 6 3, 6 4, 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 117
Figure 37.
March 2005 118
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-16Multiplex Write Mode T2 T3 T4 T5
1-16 Cycles
EX_CLK
Trecov Taddsetup Valid Address
HPI-16 Multiplexed Write Mode
EX_CS_N[0] (hcs_n)
EX_ADDR[23:0] (hcntl)
EX_RD_N (hr_w_n)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
EX_RDY_N (hrdy)
Tdata_setup Valid Data
Tdata_hold
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
EX_DATA[15:0] (hdin)
B3743-001
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 61.
HPI-16 Multiplexed Read Accesses Values
Symbol Parameter Min. Max. Units Notes
Tadd_setup Tcs2hds1val Thds1_pulse Tdata_setup Trecov
Valid time that address is asserted on the line. The address is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe being active. Pulse width of the HDS1 data strobe. Data is valid from the time from of the falling edge of HDS1_N to when the data is read. Time required between successive accesses on the expansion interface.
11 3 4 4 2
45 4 5 5 17
Cycles Cycles Cycles Cycles Cycles
1, 5, 6 5, 6 2, 4, 5 3, 5, 6 4, 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-active. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 119
Figure 38.
March 2005 120
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-16Multiplex ReadMode T2 T3 T4
T5
1-16 Cycles
HPI-16 Multiplex Read Mode
EX_CLK
Trecov Taddsetup Valid Address
EX_CS_N[0] (hcs_n)
EX_ADDR[23.0] (hcntl)
EX_RD_N (hr_w_n)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
Tdata_setup Valid Data
EX_RDY_N (hrdy)
EX_DATA[15:0] (hdout)
B3741-001
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 62.
HPI-16 Simplex Read Accesses Values
Symbol Parameter Min. Max. Units Notes
Tadd_setup Tcs2hds1val Thds1_pulse Tdata_setup Trecov
Valid time that address is asserted on the line. The address is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe being active. Pulse width of the HDS1 data strobe. Data is valid from the time from of the falling edge of HDS1_N to when the data is read. Time required between successive accesses on the expansion interface.
11 3 4 4 2
45 4 5 5 17
Cycles Cycles Cycles Cycles Cycles
1, 5, 6 5, 6 2, 4, 5 3, 5, 6 4, 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 121
Figure 39.
March 2005 122
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-16 Simplex Read Mode T2 T3 T4
T5
1-16 Cycles
HPI-16 Simplex Read Mode
EX_CLK
Trecov Taddsetup Valid Address
EX_CS_N[0] (hcs_n)
EX_ADDR[23:0] (hcntl)
EX_RD_N (hr_w_n)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
Tdata_setup Valid Data
EX_RDY_N (hrdy)
EX_DATA[15:0] (hdout)
B3744-001
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 63.
HPI-16 Simplex Write Accesses Values
Symbol Parameter Min. Max. Units Notes
Tadd_setup Tcs2hds1val Thds1_pulse Tdata_setup Tdata_hold Trecov
Valid time that address is asserted on the line. The address is asserted at the same time as chip select. Delay from chip select being active and the HDS1 data strobe being active. Pulse width of the HDS1 data strobe. Data valid prior to the rising edge of the HDS1 data strobe. Data valid after the rising edge of the HDS1 data strobe. Time required between successive accesses on the expansion interface.
11 3 4 4 4 2
45 4 5 5 36 17
Cycles Cycles Cycles Cycles Cycles Cycles
1, 5, 6 5, 6 2, 4, 5 3, 5, 6 3, 6 4, 6
Notes: 1. The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is deactive. 2. The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T clocks for setup phase. 3. The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel(R) IXP42X Product Line and Intel(R) IXC1100 Control Plane processors has had sufficient time to recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is deactive. 4. Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the Expansion Bus interface. 5. HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or T3 until HRDY is de-active. 6. One cycle is the period of the Expansion Bus clock. 7. Timing tests were performed with a 70-pF capacitor to ground.
Datasheet Document Number: 252479, Revision: 005
March 2005 123
Figure 40.
March 2005 124
T1
3-4 Cycles 3-4 Cycles 2-16 Cycles 2-4 Cycles
HPI-16Simplex Write Mode T2 T3 T4
T5
1-16 Cycles
HPI-16 Simplex Write Mode
EX_CLK
Trecov Tadd_setup Valid Address
EX_CS_N[0] (hcs_n)
EX_ADDR[23:0] (ha)
EX_RD_N (hr_w_n)
Tcs2hds1val Thds1_pulse
EX_WR_N (hds1_n)
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
Tdata_setup Valid Data
EX_RDY_N (hrdy)
EX_DATA[15:0] (hdin)
B3745-001
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.7.1
EX_IOWAIT_N
The EX_IOWAIT_N signal is available to be shared by devices attached to Chip Selects 0 through 7 and is used as required by slow devices. If the external device asserts EX_IOWAIT_N during the strobe phase of a read transfer, the controller will hold in that phase until the EX_IOWAIT_N goes false. At that time, the controller will immediately transition to the hold phase regardless of the setting of the programming parameter (T3) for the strobe phase. The EX_IOWAIT_N signal only affects the interface during the strobe phase of a read transfer. If Chip Selects 4 through 7 are configured in HPI mode of operation, each chip select will have a corresponding HRDY signal called EX_RDY. The polarity of the ready signal is programmable. Chip Select 4 corresponds to EX_RDY signal 0 and Chip Select 7 corresponds to EX_RDY signal 3.
5.5.2.8
Figure 41.
High-Speed, Serial Interfaces
High-Speed, Serial Timings
T2 T9
As Inputs: hss_txclk/ hss_rxclk1 hss_(tx or rx)frame
(Positive edge)
T1
T3
T4
hss_(tx or rx)frame
(Negative edge)
hss_ rxdata
(Positive edge)
Valid Data Valid Data
hss_ rxdata
(Negative edge) T5 T6
As Outputs: hss_(tx or rx)frame
(Positive edge)
T7
T8
hss_(tx or rx)frame
(Negative edge)
hss_ txdata
(Positive edge)
Valid Data Valid Data
hss_ txdata
(Negative edge)
A9594-01
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 64.
High-Speed, Serial Timing Values
Symbol Parameter Min. Max. Units Notes
T1 T2 T3 T4 T5 T6 T7 T8 T9
Setup time of HSS_TXFRAME, HSS_RXFRAME, and HSS_RXDATA prior to the rising edge of clock Hold time of HSS_TXFRAME, HSS_RXFRAME, and HSS_RXDATA after the rising edge of clock Setup time of HSS_TXFRAME, HSS_RXFRAME, and HSS_RXDATA prior to the falling edge of clock Hold time of HSS_TXFRAME, HSS_RXFRAME, and HSS_RXDATA after the falling edge of clock Rising edge of clock to output delay for HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA Falling edge of clock to output delay for HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA Output Hold Delay after rising edge of final clock for HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA Output Hold Delay after falling edge of final clock for HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA HSS_TXCLK period and HSS_RXCLK period
5 0 5 0 15 15 0 0 1/8.192 MHz 1/512 KHz
ns ns ns ns ns ns ns ns ns
1, 2, 3 1, 2, 3 1, 2, 3 1, 2, 3 1, 4 1, 3, 4 1, 3, 4 1, 3, 4 5
Notes: 1. HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the IXP42X product line and IXC1100 control plane processors. The signals are shown to be synchronous for illustrative purposes and are not required to be synchronous. 2. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source as inputs into the IXP42X product line and IXC1100 control plane processors. Always applicable to HSS_RXDATA. 3. The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK. 4. Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X product line and IXC1100 control plane processors to an external source. Always applicable to HSS_TXDATA. 5. The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X product line and IXC1100 control plane processors. The slowest clock speed that can be accepted or driven is 512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock duty cycle accepted will be 50/50 + 20%. 6. Timing tests were performed with a 70-pF capacitor to ground and a 10-K pull-up resistor.
For more information on the HSS Jitter Specifications see the Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer's Manual.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.5.2.9
Figure 42.
JTAG
Boundary-Scan General Timings
Tbsel Tbsch
JTG_TCK
JTG_TMS, JTG_TDI
Tbsis Tbsih
JTG_TDO
Tbsoh Tbsod
B0416-01
Figure 43.
Boundary-Scan Reset Timings
JTG_TRST_N
Tbsr
JTG_TMS
Tbsrs Tbsrh
A9597-01
Table 65.
Boundary-Scan Interface Timings Values
Symbol Parameter Conditions Min. Typ. Max. Units Notes
Tbscl Tbsch Tbsis Tbsih Tbsoh Tbsod Tbsr Tbsrs Tbsrh
JTAG_TCK low time JTAG_TCK high time JTAG_TDI, JTAG_TMS setup time to rising edge of JTAG_TCK JTAG_TDI, JTAG_TMS hold time from rising edge of JTAG_TCK JTAG_TDO hold time after falling edge of JTAG_TCK JTAG_TDO clock to output from falling edge of JTAG_TCK JTAG_TRST_N reset period JTAG_TMS setup time to rising edge of JTAG_TRST_N JTAG_TMS hold time from rising edge of JTAG_TRST_N
50 50 10 10 1.5 40 30 10 10
ns ns ns ns ns ns ns ns ns
2 2
1 1
Notes: 1. Tests completed with a TBD pF load to ground on JTAG_TDO. 2. JTAG_TCK may be stopped indefinitely in either the low or high phase.
Datasheet Document Number: 252479, Revision: 005
March 2005 127
5.5.3
Figure 44.
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Reset Timings
Reset Timings
VCCP VCC PLL_LOCK
PWRON_RESET_N RESET_IN_N EX_ADDR[23:0] CFG Settings To Be Captured TRELEASE_PWRON_RST_N TEX_ADDR_SETUP TRELEASE_RST_N TPLL_LOCK TEX_ADDR_HOLD CFG Settings To Be Captured IXP42X/IXC1100 Drives Outputs
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Document Number: 252479, Revision: 005
EX_ADDR[23:0]-Pull Up/Down
B1679-03
Datasheet
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 66.
Reset Timings Table Parameters
Symbol Parameter Min. Typ. Max. Units Note
TRELEASE_PWRON_RST_N
Minimum time required to hold the PWRON_RST_N at logic 0 state after stable power has been applied to the IXP42X product line and IXC1100 control plane processors. When using a crystal to drive the processors' system clock. (OSC_IN and OSC_OUT) Minimum time required to hold the RESET_IN_N at logic 0 state after PWRON_RST_N has been released to a logic 1 state. The RESET_IN_N signal must be held low when the PWRON_RST_N signal is held low. Maximum time for PLL_LOCK signal to drive to logic 1 after RESET_IN_N is driven to logic 1 state. The boot sequence does not occur until this period is complete. Minimum time for the EX_ADDR signals to drive the inputs prior to RESET_IN_N being driven to logic 1 state. This is used for sampling configuration information. Minimum/maximum time for the EX_ADDR signals to drive the inputs prior to PLL_LOCK being driven to logic 1 state. This is used for sampling configuration information. Minimum time required to drive RESET_IN_N signal to logic 0 in order to cause a reset after the IXP42X product line and IXC1100 control plane processors has been in normal operation. The power must remain stable and the PWRON_RST_N signal must remain stable.
500
ms
1
TRELEASE_RESET_IN_N
10
ns
TPLL_LOCK
10
s
TEX_ADDR_SETUP
50
ns
2
TEX_ADDR_HOLD
0
20
ns
2
TWARM_RESET
500
ns
Notes: 1. TRELEASE_PWRON_RST_N is the time required for the internal oscillator to reach stability. When an external oscillator is being used in place of a crystal, the 500-ms delay is not required. 2. The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals must be active until PLL_LOCK is active. 3. PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after the watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
5.6
Power Sequence
The 3.3-V I/O voltage (VCCP) must be powered up 1 s before the core voltage (VCC). The IXP42X product line and IXC1100 control plane processors' core voltage (VCC) must never become stable prior to the 3.3-V I/O voltage (VCCP). The VCCOSC, VCCPLL1, and VCCPLL2 voltages follow the VCC power-up pattern. The VCCOSCP follows the VCCP power-up pattern. The value for TPOWER_UP must be at least 1 s. The TPOWER_UP timing parameter is measured from VCCP at 3.3 V and VCC at 1.3 V. There are no power-down requirements for the IXP42X product line and IXC1100 control plane processors.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 45.
Power-Up Sequence Timing
VCCP
TPOWER_UP
4 V O L T S 3 2 1
VCC
Time
B2263-01
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Datasheet Document Number: 252479, Revision: 005
Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
5.7
Table 67.
ICC and Total Average Power
ICC and Total Average Power - Commercial Temperature Range
Speed Symbol Description Typical Current and Power1 Max Current2 Average Max Power2
Icc 266 MHz Iccp
PTOTAL
Core supply current I/O supply current Total average power both supplies Core supply current I/O supply current Total average power both supplies Core supply current I/O supply current Total average power both supplies
0.70A 0.17A
0.725A 0.26A
1.0W 0.9W
1.5W
1.9W
Icc 400 MHz Iccp
PTOTAL
0.75A 0.17A
0.800A 0.26A
1.09W 0.9W
1.57W
2.0W
Icc 533 MHz Iccp
PTOTAL
0.82A 0.17A
1.00A 0.26A
1.4W 0.9W
1.66W
2.3W
Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel(R) IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux* on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC =1.327V, VCCP = 3.363 V. Typical operating temperature is room temperature. 2. Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V, VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and ICCP are steady state currents at maximum operating temperature.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Table 68.
ICC and Total Average Power - Extended Temperature Range
Speed Symbol Description Typical Current and Power1 Max. Current2 Average Max. Power2
Icc 266 MHz Iccp
PTOTAL
Core supply current I/O supply current Total average power both supplies Core supply current I/O supply current Total average power both supplies Core supply current I/O supply current Total average power both supplies
0.70A 0.17A 1.5W 0.75A 0.17A 1.57W 0.82A 0.17A 1.66W
0.95A 0.26A
1.3W 0.9W 2.2W
Icc 400 MHz Iccp
PTOTAL
1.05A 0.26A
1.43W 0.9W 2.33W
Icc 533 MHz Iccp
PTOTAL
1.15A 0.26A
1.57W 0.9W 2.47W
Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel(R) IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC = 1.327 V, VCCP = 3.363 V. Typical operating temperature is room temperature. 2. Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V, VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and ICCP are steady state currents at maximum operating temperature.
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
6.0
Ordering Information
For ordering information, please contact your local Intel sales representative.
Datasheet Document Number: 252479, Revision: 005
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Intel(R) IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Datasheet Document Number: 252479, Revision: 005

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